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Rapid Prototype Fabrication of Custom Chip Scale Packages

  • Megan M. Owens (a1), Joseph W. Soucy (a1), Thomas F. Marinis (a1) and Henry G. Clausen (a1)

Many new electronic systems require very high-density packaging to meet system volume and weight constraints. The Chip Scale Package (CSP) is often used to meet this need. However, the limited commercial availability of die in CSP form frequently drives system designers to pursue custom CSP fabrication. Long lead times and manufacturers' reluctance to run small batches typically limit the use of custom CSPs to high volume applications. This paper presents an approach for the rapid prototype of Low Temperature Co-fired Ceramic (LTCC) CSPs.

Integral to the approach is the concept of using a small family of generic substrate designs to build a large variety of CSPs. The generic substrates may be fabricated and kept on hand until a CSP application need arises. When it does, a 12-to-16-week industry-typical lead time does not apply; the CSP may be fabricated rapidly, on site. Fabrication consists of simply singulating the substrate, populating the solder ball pads, mounting and wire bonding the die, encapsulating the substrate surface, and laser marking the assembly. The lead time may be slashed from several months to just a few days.

The family of substrate designs will be described. The substrates, with gold-based interconnects, have standard JEDEC Ball Grid Array (BGA) footprints of either 0.8 mm or 1.0 mm pitch. Substrates have a top surface metallization scheme of either a large central die bond pad surrounded by a number of peripheral bond sites for wire bonds, or a blanket metallization layer that may be patterned, via photolithography, to accommodate a specific application at the time of need. The die pad design is used for CSPs with a single die, while the blanket metallization design is patterned for hybrid or multi-die applications. The design approach, custom photopatterning and gold etch, and assembly processes are presented.

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1. Soucy Joseph W., Haley Jason F., and Marinis Thomas F., Proceedings of the 2000 International Symposium on Microelectronics, pp. 768771, September 20–22, 2000.
2. Marinis Ryan T., “Formic Acid Aided Fluxless Solder Reflow in Laboratory Setting,” Proceedings of the Student Symposium on Mechanics and Packaging (SSMP 2003), WPI, Worcester, MA, pp. 4344, 2–3 May 2003.
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MRS Online Proceedings Library (OPL)
  • ISSN: -
  • EISSN: 1946-4274
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