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Rapid Thermal Annealing of Ion Implanted p-n Junction in Silicon

Published online by Cambridge University Press:  26 February 2011

C. Ho ,
R. Kwor ,
C. Araujo  and
J. Gelpey
C. Ho
Affiliation:
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556
R. Kwor
Affiliation:
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556
C. Araujo
Affiliation:
Department of Electrical Engineering, University of Colorado at Colorado Springs, Colorado Springs, CO 80933 Eaton Corporation, Beverly, MA 01915
J. Gelpey
Affiliation:
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556
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Abstract

The rapid thermal annealing (RTA) of p+n and n+p diodes, fabricated by the LOCOS process, and its subsequent effects on junction leakage current, junction depth and dopant activation were investigated. The reverse bias diode leakage currents of implanted Si <100> samples (As+: 60 KeY, 5×1014 5×1015 cm−2, B+: 25 KeV, l×1014, l×1015 cm−2 and BF2+: 45 KeV, 1×1015cm−2 ) were measured as functions of annealing temperature, and dwell time. The annealing was performed using an Eaton RTA system (Nova ROA-400) at temperatures ranging from 950 °C to 1150 °C. Annealing times ranged from 0.2 sec. to 10 sec. The results from the diode leakage current analysis are correlated with those from Secondary Ion Mass Spectroscopy (SIMS) and differential Hall measurements. The reverse-biased leakage currents from the RTA-treated samples are compared with those from furnace-annealed samples.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 52: Symposium B – Rapid Thermal Processing , 1985 , 225
Copyright
Copyright © Materials Research Society 1986

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