Interest in CoSi2 as a metallization for very large scale integrated circuits (VLSI) has grown rapidly since the recent demonstration of a simple self-aligned process performed by rapid thermal annealing.1-4 Using a rapid thermal anneal (RTA) to directly silicide Co on Si yields smooth low-sheet-resistance films with little or no lateral diffusion and low contact resistance. In addition, it has been shown that rapid thermal annealing can result in reasonable quality epitaxial CoSi2 on (111) Si wafers.5 An important advantage of CoSi2 over the more commonly used TiSi2 metallization is the relative simplicity of its self-aligned silicidation process. Due to the low reactivity of Co with SiO2, a simple two-step self-alignment process is possible instead of the three-step process necessary with TiSi2.6 The primary disadvantage of CoSi2 is the amount of Si consumed for equal silicide sheet resistance. For example, to yield a silicide sheet resistance of 1.5 1/LD, Van den Hove 4 finds that compared to the TiSi, process, the CoSi, process would consume an additional 24 nm of Si. (This disadvantage can be minimized if very shallow junctions can be formed under the CoSi2.)