Hostname: page-component-76fb5796d-vfjqv Total loading time: 0 Render date: 2024-04-29T12:55:53.224Z Has data issue: false hasContentIssue false

Multilayer memristive/memcapacitive devices with engineered conduction fronts

Published online by Cambridge University Press:  13 June 2013

Patrick R. Mickel*
Affiliation:
Sandia National Laboratories, P.O. Box 5800, Albuquerque, New Mexico 87185, USA
Conrad D. James
Affiliation:
Sandia National Laboratories, P.O. Box 5800, Albuquerque, New Mexico 87185, USA
*
Get access

Abstract

We present a novel multilayered architecture for memristive devices which provides an alternative to conventional conductive filament switching. In conventional resistive switching, conductive filaments form and extend stochastically under applied electrical bias, with longer filaments being subjected to magnified electric fields that amplify their growth rate, producing a spatially localized and highly non-uniform conduction front of filaments. This produces devices with large variations in resistive and capacitive properties that are difficult to tune. Here, we simulate a multilayered device structure with alternating ionic mobility that predicts the development of a quasi-uniform conduction front which amplifies memcapacitive properties of the device and reduces device-to-device variability. Furthermore, this novel structure is predicted to enable fine-tuned control of switching events, an important property for analog (multibit) memory and neuromorphic computing applications.

Type
Research Article
Copyright
© EDP Sciences, 2013

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Liu, Q. et al., ACS Nano 4, 6162 (2010)CrossRef
Waser, R., Aono, M., Nat. Mater. 6, 833 (2007)CrossRef
Wong, H.P. et al., Proc. IEEE 98, 2201 (2010)CrossRef
Ramirez, A.P., J. Phys.: Condens. Matter 9, 8171 (1997)
Burr, G.W. et al., IBM J. Res. Devel. 52, 449 (2008)CrossRef
Waser, R. et al., Adv. Mat. 21, 2632 (2009)CrossRef
Hickmott, T.W., J. Appl. Phys. 33, 2669 (1962)CrossRef
Gibbons, J.F., Beadle, W.E., Solid-State Electron. 7, 785 (1964)CrossRef
Strukov, D.B. et al., Nature 453, 80 (2008)CrossRef
Chua, L.O., Sung Mo, K., Proc. IEEE 64, 209 (1976)CrossRef
Chua, L., IEEE Trans. Circuit Theory 18, 507 (1971)CrossRef
Chang, T., Jo, S.-H., Lu, W., ACS Nano 5, 7669 (2011)CrossRef
Jo, S.H. et al., Nano Lett. 10, 1297 (2010)CrossRef
Snider, G.S., Spike-timing-dependent learning in memristive nanodevices, in IEEE International Symposium on Nanoscale Architectures, NANOARCH 2008, Anaheim, CA, USA, 2008Google Scholar
Pershin, Y.V., Di Ventra, M., Proc. IEEE 100, 2071 (2012)CrossRef
Kwon, D.-H. et al., Nat. Nano. 5, 148 (2010)CrossRefPubMed
Yang, J.J. et al., Nat. Nano. 3, 429 (2008)CrossRef
Yang, Y.C. et al., Nano. Lett. 9, 1636 (2009)CrossRef
Tanaka, H. et al., AIP Adv. 2, 022141 (2012)CrossRef
Sheridan, P. et al., Nanoscale 3, 3833 (2011)CrossRef
Russo, U. et al., IEEE Trans. Electron Devices 56, 1040 (2009)CrossRef
Strukov, D., Williams, R., Appl. Phys. A: Mater. Sci. Process. 94, 515 (2009)CrossRef
Dimin, N. et al., Impact of process variations on emerging memristor, in 47th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, 2010Google Scholar
Jing, H., Tahoori, M.B., Lombardi, F., in 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, 2004
Di Ventra, M., Pershin, Y.V., Chua, L.O., Proc. IEEE 97, 1717 (2009)CrossRef
Krems, M., Pershin, Y.V., Di Ventra, M., Nano Lett. 10, 2674 (2010)CrossRef
Martinez-Rincon, J., Di Ventra, M., Pershin, Y.V., Phys. Rev. B 81, 195430 (2010)CrossRef
Pershin, Y.V., Di Ventra, M., Adv. Phys. 60, 145 (2011)CrossRef
Driscoll, T. et al., Science 325, 1518 (2009)CrossRef
Siles, P.F. et al., Nanotechnology, 24 035702 (2013)CrossRef