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Impact of maximum copper content during the 3-stage process on CdS thickness tolerance in Cu(In,Ga)Se2-based solar cell

Published online by Cambridge University Press:  12 September 2013

Thomas Lepetit ,
Ludovic Arzel  and
Nicolas Barreau
Thomas Lepetit
Affiliation:
Institut des Matériaux Jean Rouxel (IMN), Université de Nantes, CNRS – UMR 6502 2 rue de la Houssinière, BP 32229, 44322 Nantes cedex 3, France
Ludovic Arzel
Affiliation:
Institut des Matériaux Jean Rouxel (IMN), Université de Nantes, CNRS – UMR 6502 2 rue de la Houssinière, BP 32229, 44322 Nantes cedex 3, France
Nicolas Barreau
Affiliation:
Institut des Matériaux Jean Rouxel (IMN), Université de Nantes, CNRS – UMR 6502 2 rue de la Houssinière, BP 32229, 44322 Nantes cedex 3, France
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Abstract

The tolerance of photovoltaic performances of Cu(In,Ga)Se2-based (CIGSe) solar cells prepared from 3-stage grown absorbers to cadmium sulfide (CdS) buffer layer thickness was investigated. We focus on the influence of the maximum Cu content y = [Cu]/([In]+[Ga]) reached during the co-evaporation process on this tolerance. By increasing the duration of the 2nd stage we varied ymax from 0.93±0.11 up to 1.06±0.12. Although final Cu content and CIGSe surface morphology seem to be similar for all absorbers, the photovoltaic performance of cells with higher maximum Cu content are better; moreover they tolerate much thinner CdS buffers (down to 10 nm-thick) without open circuit voltage or fill factor loss. Cells with lower ymax exhibit more erratic performance and J(V,T) measurements show a specific voltage distribution for thin CdS. From these results it appears possible to decrease the CdS buffer layer thickness if it is deposited on adapted absorbers.

Keywords

photovoltaicCuphysical vapor deposition (PVD)
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1538: Symposium C – Compound Semiconductors: Thin-Film Photovoltaics, LEDs and Smart Energy Controls , 2013 , pp. 33 - 38
Copyright
Copyright © Materials Research Society 2013 

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References

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