Hostname: page-component-76fb5796d-22dnz Total loading time: 0 Render date: 2024-04-26T11:48:52.033Z Has data issue: false hasContentIssue false

Metal Suppression of Pentacene Grain Growth

Published online by Cambridge University Press:  01 February 2011

Hsi-wen Lo
Affiliation:
lo@mems.caltech.edu, California Institute of Technology, Electrical Engineering, 1200 E. California Blvd, Pasadena, CA, 91125, United States
Yu-Chong Tai
Affiliation:
yctai@caltech.edu, California Institute of Technology, Pasadena, CA, 91125, United States
Get access

Abstract

Pentacene thin-film transistors use either bottom-contact or top-contact electrodes. Transistors with bottom-contact electrodes are fabricated in such a way that metal is deposited and patterned before pentacene deposition while those with top-contact electrodes are fabricated in reverse order. Hole mobility is closely related to pentacene grain sizes and grain sizes of pentacene depend heavily on the surface roughness. When the surfaces are flat and smooth enough, the grains of pentacene are still small if metal is deposited before pentacene, i.e., bottom-contact configuration. Pentacene inside the channels formed by source and drain electrodes has much smaller grains than those far away from metal electrodes.

To further understand this phenomenon, we first studied pentacene grain growth on different substrates (oxide, Poly-4-vinylphenol or PVP, and SU8-2.) but with same metal electrodes (500 Ö Au). Next, we studied pentacene grain growth on the same substrate (oxide) but with different metal electrodes (500 Ö Au, 500 Ö Al, and 500 ÖCr). To avoid contaminating and damaging substrate surfaces, we used shadow masks for metal deposition.

For substrate studies, the fabrication process of testing samples began by oxidation of silicon wafers. PVP and SU8-2 were spin-coated on oxide wafers and cured. 500 Ö Au was thermally evaporated through shadow masks onto wafers to form source and drain. Pentacene was then thermally evaporated onto the wafers.

Likewise, the fabrication process of the second study began by oxidation of silicon wafers. Different metals were thermally evaporated through shadow masks onto oxide wafers. Finally, pentacene was thermally evaporated onto the wafers.

To further study the relation between pentacene grain sizes and distance from metal electrodes, we also made metal ring structures. The substrates were kept at room temperature during pentacene deposition for all samples.

Grain diameters were calculated from scanning probe microscopic or atomic force microscopic images. Images taken with Veeco Digital Instrument Dimension 3100 AFM were analyzed with Scion Image program. After counting particle numbers, average grain diameters were calculated assuming grains are circular.

Our data show that pentacene has drastically smaller grains inside the channels electrodes than that far away electrodes for all 3 kinds of substrates: oxide, PVP and SU8-2. EDS spectrum confirms that there is no Au inside the channels. Not only Au, but also Al and Cr show the same phenomenon. Across the 400-um metal rings, pentacene grain diameters increase first and then decrease, confirming that pentacene grain growth is somehow suppressed by the presence of metal.

This phenomenon adds another reason supporting that pentacene thin-film transistors with bottom-contact electrodes have worse performances due to smaller grains. Currently, we are working on modeling this phenomenon and finding theoretical explanations.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Garnier, F., Kouli, F., Hajlaoui, R., and Horowitz, G., “Tunneling at organic/metal interfaces in oligomer-based thin-film transistorsfl, MRS Bull., pp5256, June, 1997 Google Scholar
2. Steudel, S., Vusser, S. D., Jonge, S. D., Janssen, D., Verlaak, S., Genoe, J., and Hermans, P., “Influence of the dielectric roughness on the performance of pentacene transistors”, Applied Physics Letter, Vol 85, No 19, 2004.10.1063/1.1815042Google Scholar