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Offset-Gate Structures for Increased Breakdown Voltages in Silicon-On-Insulator Transistors

Published online by Cambridge University Press:  21 February 2011

C. I. Drowley  and
T. I. Kamins
C. I. Drowley
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
T. I. Kamins
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
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Abstract

An offset-gate structure was used to fabricate p-channel MOS transistors in laser-recrystallized silicon-on-insulator (SOI) films. The breakdown voltage increased from about -18 V with a conventional gate structure to about -38 V with the offset gate and was then limited by bulk breakdown in the film, rather than by the high fields near the gate drain overlap region. Simulations indicate that breakdown voltages of about -60 V can be achieved in the structure used, provided that the back-surface fixed-charge density is limited to 1×10″ cm−2.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 33: Symposium D – Comparison of Thin Film Transistor and SOI Technologies , 1984 , 133
Copyright
Copyright © Materials Research Society 1984

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References

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