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Mixed-Ionic-Electronic-Conduction (MIEC)-Based Access Devices for 3D Multilayer Crosspoint Memory

Published online by Cambridge University Press:  09 February 2015

Kumar Virwani ,
Geoffrey W. Burr ,
Pritish Narayanan  and
Bülent Kurdi
Kumar Virwani*
Affiliation:
IBM Research – Almaden, 650 Harry Road, San Jose, California 95120
Geoffrey W. Burr
Affiliation:
IBM Research – Almaden, 650 Harry Road, San Jose, California 95120
Pritish Narayanan
Affiliation:
IBM Research – Almaden, 650 Harry Road, San Jose, California 95120
Bülent Kurdi
Affiliation:
IBM Research – Almaden, 650 Harry Road, San Jose, California 95120
*
*Email: kvirwan@us.ibm.com
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Abstract

A number of applications call for the organization of resistive non-volatile memory (NVM) into large, densely-packed crossbar arrays. While resistive-NVM devices often possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (>1000×1000 device) arrays at low power tends to require large (> 1e7) ON-to-OFF ratios between the currents passed at high and at low voltages. Such large nonlinearities can be implemented by including a distinct access device together with each of the state-bearing resistive-NVM elements. While such an access device need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device.

We review our work on high-performance access devices based on Cu-containing Mixed-Ionic-Electronic Conduction (MIEC) materials [1–7]. (This version focuses only on the MIEC-based access device itself; previously-published longer versions of this work [8–10] also include more extensive surveys of competing devices as well.) These devices require only the low processing temperatures of the Back-End-Of-the-Line (BEOL), making them highly suitable for implementing multi-layer crossbar arrays. MIEC-based access devices offer large ON/OFF ratios (>1e7), a significant voltage margin Vm (over which current < 10nA), and ultra-low leakage (<10pA), while also offering the high current densities needed for PCM and the fully bipolar operation needed for high-performance RRAM. Scalability to critical dimensions (CD) <30nm and thicknesses <15nm, tight distributions and 100% yield in large (512kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based access devices shows that their operation depends on Cu+ mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low (<1.2V) switching voltages, a compact vertical stack of two MIEC devices in series could support large crossbar arrays for switching voltages up to 2.5V.

Keywords

memorydevicesionic conductor
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1729: Symposium M – Materials and Technology for Nonvolatile Memories , 2015 , pp. 3 - 14
Copyright
Copyright © Materials Research Society 2015 

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