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Nanometer Lithography for Quantum Scale Devices

Published online by Cambridge University Press:  25 February 2011

Charles F. Cook Jr.
Affiliation:
US Army Electronics Technology and Devices Laboratory (LABCOM), Fort Monmouth, NJ 07703-5000 (201) 544-4581
Joseph H. Kwiatkowski
Affiliation:
US Army Electronics Technology and Devices Laboratory (LABCOM), Fort Monmouth, NJ 07703-5000 (201) 544-4581
Doran D. Smith
Affiliation:
US Army Electronics Technology and Devices Laboratory (LABCOM), Fort Monmouth, NJ 07703-5000 (201) 544-4581
Harry L. Berkowitz
Affiliation:
US Army Electronics Technology and Devices Laboratory (LABCOM), Fort Monmouth, NJ 07703-5000 (201) 544-4581
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Abstract

Electron-beam lithography that has the capability of writing high-resolution nanometer features in semiconductors will be required to fabricate next-generation quantum scale devices, such as nanometer gate mini-FET's, lateral quantum-well arrays, or metal grid radiators,which have feature sizes from 100 nm (1000 A) to 15 nm (150 A). A Philips EM 420T scanning transmission, electron microscope (STEM) has been modified to write nanometersize features in gallium arsenide. For this STEM we have developed a high-speed beam blanker and pattern generator (PG) that is resist speed limited. The maximum writing field size is 100 by 100 micrometers; within this field size, the smallest addressable step is approximately 1.8 nm (18 A). A HP-9845 is used to supply data for the PG and for computer-aided design of the devices to be written. Pattern transfer from the resist to GaAs is completed by using the liftoff method. As a result of this capability, we have patterned more than one million dots in a prototype 80 by 80 micrometer solid state radiator. The dots have diameters down to 15 nm (150 A), which requires an e-beam writing time of less than 30 minutes.

Type
Articles
Copyright
Copyright © Materials Research Society 1987

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References

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