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Characterization of Graphene Gate Electrodes for Metal-Oxide-Semiconductor Devices

Published online by Cambridge University Press:  19 January 2017

Yanbin An
Affiliation:
Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611USA.
Aniruddh Shekhawat
Affiliation:
Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611USA. Department of Materials Science and Engineering, University of Florida, Gainesville, FL 32611USA.
Ashkan Behnam
Affiliation:
Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801USA.
Eric Pop
Affiliation:
Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801USA.
Ant Ural*
Affiliation:
Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611USA.
*
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Abstract

We fabricate and characterize metal-oxide-semiconductor (MOS) devices with graphene as the gate electrode, 5 or 10 nm thick silicon dioxide as the insulator, and silicon as the semiconductor substrate. We find that Fowler-Nordheim tunneling dominates the gate current for the 10 nm oxide device. We also study the temperature dependence of the tunneling current in these devices in the range 77 to 300 K and extract the effective tunneling barrier height as a function of temperature for the 10 nm oxide device. Furthermore, by performing high frequency capacitance-voltage measurements, we observe a local capacitance minimum under accumulation, particularly for the 5 nm oxide device. By fitting the data using numerical simulations based on the modified density of states of graphene in the presence of charged impurities, we show that this local minimum results from the quantum capacitance of graphene. These results provide important insights for the heterogeneous integration of graphene into conventional silicon technology.

Type
Articles
Copyright
Copyright © Materials Research Society 2017 

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References

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