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2 - Probabilistic Forecasting of Power System and Market Operations
- from Part I - Statistical Learning
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- By Yuting Ji, Lang Tong, Weisi Deng
- Edited by Ali Tajer, Rensselaer Polytechnic Institute, New York, Samir M. Perlaza, H. Vincent Poor, Princeton University, New Jersey
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- Book:
- Advanced Data Analytics for Power Systems
- Published online:
- 22 March 2021
- Print publication:
- 08 April 2021, pp 28-51
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- Chapter
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Summary
The increasing penetration of renewable resources has changed the characteristics of power system and market operations, from one relying primarily on deterministic and static planning to one involving highly stochastic and dynamic operations. In such new operation regimes, the ability of adapting changing environments and managing risks arising from complex scenarios of contingencies is essential. To this end, an operation tool that provides probabilistic forecasting that characterizes the underlying probability distribution of variables of interest can be extremely valuable. A fundamental challenge in probabilistic forecasting for system and market operations is the scalability. As the size of system and the complexity of stochasticity increase, standard techniques based on direct Monte Carlo and machine learning techniques become intractable. This chapter outlines an alternative approach based on an online learning to overcome barriers of computation complexity.
High-Productivity Combinatorial PVD and ALD Workflows for Semiconductor Logic & Memory Applications
- Imran Hashim, Chi-I Lang, Hanhong Chen, Jinhong Tong, Monica Mathur, Prashant Phatak, Ronald Kuse, Sandra Malhotra, Sunil Shanker, Xiangxin Rui
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- Journal:
- MRS Online Proceedings Library Archive / Volume 1159 / 2009
- Published online by Cambridge University Press:
- 31 January 2011, 1159-G01-02
- Print publication:
- 2009
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- Article
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With materials innovation driving recent logic and memory scaling in the semiconductor industry, High-Productivity Combinatorial™ (HPC) technology can be a powerful tool for finding optimum materials solutions in a cost-effective and efficient manner. This paper will review unique HPC wet processing, physical vapor deposition (PVD), and atomic layer deposition (ALD) capabilities that were developed, enabling site-isolated testing of multiple conditions on a single 300mm wafer. These capabilities were utilized for exploration of new chalcogenide alloys for phase change memory, and for metal gate and high-K dielectric development for high-performance logic. Using an HPC PVD chamber, a workflow was developed in which up to 40 different precisely controlled GeSbTe alloy compositions can be deposited in discrete site-isolated areas on a single 300mm wafer and tested for electrical & material properties, using a custom in-situ high-throughput sheet-resistance measurement setup, to get very accurate measurements of the amorphous – crystalline transition temperature. We will review how resistivity as a function of temperature, crystallization temperature, final and intermediate (if any) crystalline phases were mapped for a section of the GeSbTe phase diagram, using only a few wafers. Another area where HPC can be very valuable is for finding optimum materials for high-k dielectrics and metal gates for high-performance logic transistors. Assessing the effective work-function (EWF) for a given high-k dielectric metal-gate stack for PFET and NFET transistors is a critical step for selecting the right materials before further integration. One way to obtain EWF is by using a terraced oxide wafer with different SiO2 thickness bands underneath the high-k dielectric. We report a HPC workflow using our wet, ALD & PVD capabilities, to quickly assess EWF for multiple different high-k dielectrics and metal gate stacks. This workflow starts with a HPC wet etch of thermal silicon oxide, creating different oxide thicknesses 1–10nm in select areas of the same substrate. This is followed by atomic layer deposition of a high-k dielectric film such as HfO2. Next, a metal e.g., TaN is deposited through a physical mask or patterned post-deposition to complete the formation of MOS capacitors. The final step is C-V measurements and C-V modeling to extract Vfb, high-k dielectric constant, EOT, and EWF from Vfb vs EOT plot. This workflow was used to extract EWF for a TaN metal gate with an ALD HfO2 high-k dielectric using a metal-organic precursor. We will discuss how EWF for this system was affected by annealing post-dielectric deposition & post-metallization, different annealing temperatures & ambients, Hf pre-cursors and interfacial cap layers e.g., La2O3 & Al2O3. Finally, we will also discuss more advanced versions of this workflow where the ALD high-k dielectric and PVD metal gate is also varied on the same wafer using HPC versions of ALD & PVD chambers.
17 - Training for MIMO communications
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- By Youngchul Sung, Cornell University, Tae Eung Sung, Cornell University, Brian M. Sadler, U.S. Army Research Laboratory, Lang Tong, Cornell University
- Edited by H. Bölcskei, ETH Zürich, Switzerland, D. Gesbert, Eurecom Institute, C. B. Papadias, Bell Labs, Lucent Technologies, A.-J. van der Veen, Technische Universiteit Delft, The Netherlands
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- Book:
- Space-Time Wireless Systems
- Published online:
- 25 February 2010
- Print publication:
- 15 June 2006, pp 342-362
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Summary
In this chapter, an overview of training signal design for multiple-input multiple-output (MIMO) systems is provided with basic theoretical frameworks related to parameter estimation and information theory, as well as generalization and practical issues.
Introduction
Many MIMO communication systems and space-time techniques, for example, BLAST (Foschini, 1996), are designed for coherent detection, which requires channel state information for successful decoding. To facilitate channel estimation and synchronization in such systems, training or pilot signals are usually embedded in transmitted data streams. The design of these training signals can affect significantly the overall performance of a wireless system.
Since the use of training signals reduces effective data throughput, it is natural to seek optimal design of these embedded signals; one may ask “how many training symbols are necessary?” or “what is the optimal pilot sequence and its placement within data streams?”
Optimal training design for MIMO systems is a challenging task since the number of channel parameters to estimate increases rapidly as the number of transmitting and receiving antennas increases. Optimality of design depends on various factors such as receiver implementation, channel model, and design criteria. Although receiver architecture must be taken into account, training design is primarily a transmitter technique. Once a training scheme is chosen, it may be standardized for a specific application. It is therefore important that a training scheme is optimal or near optimal for a wide range of channel conditions and receiver implementations.