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2 - Characteristics, performance, modeling, and reliability of SiGe HBT technologies for mm-wave power amplifiers
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- By David Harame, Formerly of IBM, now with Global Foundries, Vibhor Jain, IBM, Renata Camillo Castillo, IBM
- Edited by Hossein Hashemi, University of Southern California, Sanjay Raman, Virginia Polytechnic Institute and State University
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- Book:
- mm-Wave Silicon Power Amplifiers and Transmitters
- Published online:
- 05 April 2016
- Print publication:
- 04 April 2016, pp 17-76
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Summary
Introduction
SiGe BiCMOS technology is an excellent choice for RF (radio frequency) and mm-wave applications as it combines the best features of CMOS logic, high-performance SiGe heterojunction bipolar transistors (SiGe HBTs), and RF passives like transmission lines, capacitors, inductors, Schottky barrier diodes (SBDs), p-i-n diodes, and resistors. RF models for all of these devices and process design kits are readily available for the design and simulation of RF circuits. In addition, BiCMOS technologies generally support multiple HBTs having different breakdown voltage, noise, and performance specifications for varied applications.
The selection of any technology for mm-wave applications like power amplifiers (PAs) or transmitters is dependent not only on the performance of the technology but more so on the economics and total cost of the project integration. Compound semiconductor HBTs like InP and GaAs have better cut-off frequencies and breakdown voltage but lose to silicon technologies in terms of cost and integration. RFCMOS technologies may have similar performance specifications to the SiGe HBTs but BiCMOS is still preferred over RFCMOS for several reasons. At the same lithography node, SiGe HBT has superior performance and breakdown voltage to the CMOS devices. For equal performance CMOS requires much more aggressive lithography (>n + 2 gen) and as such is significantly more expensive than SiGe BiCMOS. SiGe HBTs have a higher breakdown voltage and power handling capability, higher operating voltage, higher self-gain, better voltage swing, better impedance matching, and better linearity than CMOS. This chapter will explore these and other aspects of the SiGe BiCMOS technology that make it ideal for silicon mm-wave applications like power amplifiers and transmitters.
The chapter begins with a basic graded-base SiGe HBT device physics description followed by a discussion about the processing technology used to fabricate the device emphasizing aspects that impact high-performance mm-wave SiGe HBTs. A detailed comparison of performance trends across various technologies and industries is presented next. For mm-wave circuits there is an additional set of metrics such as breakdown voltage, noise figure, linearity, and thermal effects which are key to mm-wave applications. Several sections are devoted to discussion of breakdown voltage, thermal effects, and noise figure. In addition to the SiGe HBT transistors, silicon RF passives are also important and there is a discussion on Schottky diodes, PIN diodes, and other passives readily available in BiCMOS technologies.
An Alternative Approach to Analyzing the Interstitial Decay from the End of Range Damage During Millisecond Annealing
- Renata Camillo-Castillo, Mark E Law, Kevin S Jones
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- Journal:
- MRS Online Proceedings Library Archive / Volume 1070 / 2008
- Published online by Cambridge University Press:
- 01 February 2011, 1070-E06-09
- Print publication:
- 2008
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Flash-assist Rapid Thermal Processing (RTP) presents an opportunity to investigate annealing time and temperature regimes which were previously not accessible with conventional annealing techniques such as Rapid Thermal Annealing. This provides a unique opportunity to explore the early stages of the End of Range (EOR) damage evolution and also to examine how the damage evolves during the high temperature portion of the temperature profile. However, the nature of the Flash-assist RTP makes it is extremely difficult to reasonably compare it to alternative annealing techniques, largely because the annealing time at a given temperature is dictated by the FWHM of the radiation pulse. The FWHM for current flash tools vary between 0.85 and 1.38 milliseconds, which is three orders of magnitude smaller to that required for a RTA to achieve similar temperatures. Traditionally, the kinetics of the extended defects has been studied by time dependent studies utilizing isothermal anneals; in which specific defect structures could be isolated. The characteristics of Flash-assist RTP do not allow for such investigations in which the EOR defect evolution could be closely tracked with time. Since the annealing time at the target temperature for the Flash-assist RTP is essentially fixed to very small times on the order of milliseconds, isochronal anneals are a logical experimental approach to temperature dependent studies. This fact presents a challenge in the data analysis and comparison. Another feature of Flash-assist RTP which makes the analysis complex is the ramp time relative to the dwell time spent at the peak fRTP temperature. As the flash anneal temperature is increased the total ramp time can exceed the dwell time at the peak temperature, which may play a significantly larger role in dictating the final material properties. The inherent characteristics of Flash-assist RTP have consequently required the development of another approach to analyzing the attainable experimental data, such that a meaningful comparison could be made to past studies. The adopted analysis entails the selection of a reference anneal, from which the decay in the trapped interstitial density can be tracked with the flash anneal temperature, allowing for the kinetics of the interstitial decay to be extracted.
Study of the Effects of a Two-Step Anneal on the End of Range Defects in Silicon
- Renata A. Camillo-Castillo, Kevin. S. Jones, Mark E. Law, Leonard M. Rubin
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- Journal:
- MRS Online Proceedings Library Archive / Volume 717 / 2002
- Published online by Cambridge University Press:
- 01 February 2011, C1.4
- Print publication:
- 2002
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Transient enhanced diffusion (TED) is a challenge that the semi-conductor industry has been faced with for more than two decades. Numerous investigations have been conducted to better understand the mechanisms that govern this phenomenon, so that scale down can be acheived. {311} type defects and dislocation loops are known interstitial sources that drive TED and dopants such as B utilize these interstitials to diffuse throughout the Si lattice. It has been reported that a two-step anneal on Ge preamorphized Si with ultra-low energy B implants has resulted in shallower junction depths. This study examines whether the pre-anneal step has a measurable effect on the end of range defects. Si wafers were preamorphized with Ge at 10, 12, 15, 20 and 30keV at a dose of 1x1015cm-2 and subsequently implanted with 1x1015cm-2 1keV B. Furnace anneals were performed at 450, 550, 650 and 750°C; the samples were then subjected to a spike RTA at 950°C. The implant damage was analyzed using Quantitative Transmission Electron Microscopy (QTEM). At the low energy Ge preamorphization, little damage is observed. However at the higher energies the microstructure is populated with extended defects. The defects evolve into elongated loops as the preanneal temperature increases. Both the extended defect density and the trapped interstitial concentration peak at a preanneal temperature of 550°C, suggesting that this may be an optimal condition for trapping interstitials.
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