2 results
3 - Patterns
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- By G. E. Koppenwallner, D. Etling, C.-W. Leong, J. M. Ottino, E. Villermaux, J. Duplat, P. D. Weidman, V. O. Afenchenko, A. B. Ezersky, S. V. Kiyashko, M. I. Rabinovich, E. Bodenschatz, S. W. Morris, J. R. De bruyn, D. S. Cannell, G. Ahlers, C. F. Chen, F. Zoueshtiagh, P. J. Thomas, G. Gauthier, P. Gondret, F. Moisy, M. Rabaud, M. Fermigier, P. Jenffer, E. Tan, S. T. Thoroddsen, B. Vukasinovic, A. Glezer, M. K. Smith, N. J. Zabusky, W. Townsend, R. A. Hess, N. J. Brock, B. J. Weber, L. W. Carr, M. S. Chandrasekhara
- M. Samimy, Ohio State University, K. S. Breuer, Brown University, Rhode Island, L. G. Leal, University of California, Santa Barbara, P. H. Steen, Cornell University, New York
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- Book:
- A Gallery of Fluid Motion
- Published online:
- 25 January 2010
- Print publication:
- 12 January 2004, pp 28-41
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Summary
Vortex flows paint themselves
The artistlike pictures of vortex flows presented here have been produced by the flow itself. The method of this “natural” flow visualization can be described briefly as follows: The working fluid is water mixed with some paste in order to increase the viscosity. Vortex flows are produced by pulling a stick or similar devices through the fluid or by injecting fluid through a nozzle into the working tank.
The flow visualization is performed in the following way: the surface of the fluid at rest is sparkled with oil paint of different colors diluted with some evaporating chemical. After the vortex structures have formed due to wakes or jets, a sheet of white paper is placed on the surface of the working fluid, where the oil color is attached to the paper immediately. The final results are artistlike paintings of vortex flows which exhibit a rich variety of flow structures.
Mixing in regular and chaotic flows
These photographs show the time evolution of two passive tracers in a low Reynolds number two-dimensional timeperiodic flow. The initial condition corresponds to two blobs of dye, green and orange, located below the free surface of a cavity filled with glycerine. The flow is induced by moving the top and bottom walls of the cavity while the other two walls are fixed. In this experiment the top wall moves from left to right and the bottom wall moves from right to left; both velocities are of the form Usin2(2πt/T), with the same U and the same period T, but with a phase shift of 90°.
Optical Interconnection Network Co-Integration: The Potential of Optical Polymers
- L. A. Hornak, T. W. Weidman
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- Journal:
- MRS Online Proceedings Library Archive / Volume 228 / 1991
- Published online by Cambridge University Press:
- 21 February 2011, 51
- Print publication:
- 1991
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The explosive growth under way in the performance of digital electronic systems is directly traceable to the impact of Si MOS device scaling and its accompanying increase in functionality at the chip level. The increasing data rates and chip I/O that have accompanied this scaling have driven the evolution of both system architectures and the interconnection and packaging technologies (i.e. chip carriers, printed circuit boards, bus structures) that support this CMOS functionality and dominate overall system volume. The further scaling of CMOS technology towards 0.1 – 2.5μm minimum gate lengths coupled with modest increases in chip size (i.e. 2–4 cm), promise upwards of a 100 fold increase in chip-level complexity. The resulting emergence of Ultra Large Scale Integrated (ULSI) processor array chips and wafer-scale memory (solid state disks) hold the potential for extremely compact distributed computing systems. Through a continuation of the evolutionary trends of system scaling, application of chip level process technology to higher system levels, and mixed technology integration (e.g. BiCMOS); present advanced packaging technologies based upon Multi-Chip Modules (MCM) will mature into hybrid wafer-level three-dimensional silicon systems allowing burdensome driver and communication control functions now designed at the chip level to move off chip into the active silicon interconnection substrate where network transmission and control can both be implemented. Realization of the performance potential of these silicon ULSI systems will largely depend on the successful implementation of this wafer-level communication network linking the high-density of processing nodes. The role that any advanced technology (i.e. high-speed normal electronic, superconducting, optical) will serve within this network will be determined by the degree of connectivity it can achieve in this scaled environment and by its ability to benignly coexist with the dominant CMOS technology, the network's physical and functional foundation[l].