This appendix presents a stable compensation scheme for AMOLED displays based on the strong interdependence observed between the luminance degradation of OLED and its current drop under bias stress [114]. This feedback based compensation provides 30% improvement in the luminance stability under 1600-hour of accelerative stress. To employ this scheme in AMOLED displays, a new pixel circuit is presented that provides on-pixel electrical access to the OLED current without compromising the aperture ratio.

Interdependence between electrical and luminance degradation

Figure B.1 shows the lifetime results of a 4-mm2 PIN-OLED with a red phosphorescent emitter for a constant luminance of 1500 nits/cm2. A constant voltage of 3 V is applied to the OLED and the current and luminance are measured every 10 minutes. As seen, the ratio between luminance and current degradation is almost constant for the entire range. Here, ΔL and ΔI are the degradation in the OLED luminance and current, respectively, and L0 and I0 are the respective initial values. From the observed interdependence, it appears very likely that both luminance degradation and drop in the drive current in the OLED have a common source, and that may be the charge trapping/de-trapping at the interface of the different layers [12]. Thus, it is possible to control the aging of OLED using its output electrical signals. Although, there is a deviation at degradation levels higher than 60%, we adopt a linear approximation for the compensation scheme.

Design of the VPPCs that provides the required configurability for voltage programming is hindered by several issues: complexity (a lower yield and aperture ratio), extra controlling signals (more complex external drivers), and extra operating cycles (overhead in power consumption). Moreover, the limited time provided for VT generation by the conventional addressing scheme, results in imperfect compensation. This appendix reviews different methods in increasing the VT-generation time [70, 71].

Interleaved addressing scheme

The interleaved addressing scheme depicted in Figure A.1 is based on VT generation for several rows simultaneously. The rows in a panel are divided into a few segments and the VT-generation cycle is carried out for each segment. As a result, the time assigned to the VT-generation cycle is extended by the number of rows in a segment leading to more precise compensation. Particularly, since the leakage current of a-Si:H TFTs is small (of the order of 10−14), the generated VT can be stored in a capacitor and be used for several other frames (see Figure A.1). As a result, the operating cycles during the following post-compensation frames are reduced to the programming and driving cycles similar to the operation of conventional 2-TFT pixel circuit [6]. Consequently, the power consumption associated with the external driver and with charging/discharging the parasitic capacitances is divided between the same few frames. In Figure A.1, the number of frames per segment is denoted as “h” and the number of frames per compensation interval as “l”. As seen, the driving cycle of each row starts with a delay of τP from the previous row, which is the timing budget of the programming cycle. Since τP (of the order of 10 µs) is much smaller than the frame time (of the order 16 ms), the latency effect is negligible. However, to improve the brightness accuracy, one can either change the programming direction each time, so that the average brightness lost due to latency becomes equal for all the rows, or take into consideration this effect in the programming voltage of the frames before and after the compensation cycles.

Advances in thin film materials and process technologies continue to fuel new areas of application in large area electronics. However, this does not come without new issues related to device-circuit stability and uniformity over large areas, placing an even greater need for new driving algorithms, biasing techniques, and fully compensated circuit architectures. Indeed, each application is unique and mandates specific circuit and system design techniques to deal with materials and process deficiencies. As this branch of electronics continues to evolve, the need for a consolidated source of design methodologies has become even more compelling. Unlike classical circuit design approaches where trends are toward transistor scaling and high integration densities, the move in large-area electronics is toward increased functionality, in which device sizes are not a serious limitation. This book is written to address these challenges and provide system-level solutions to electronically compensate for these deficiencies.

Although the circuit and system implementation examples given are based primarily on amorphous silicon technology, the design techniques and solutions described are unique, and applicable to a wide variety of disordered materials, ranging from polysilicon and metal oxides to organic families. These are complemented by real-world examples related to active-matrix organic light emitting diode displays, bio-array sensors, and flat-panel biomedical imagers. We address mixed-phase thin film and crystalline silicon electronics and, in particular, the design and interface techniques for high and low voltage circuits in the respective design spaces. The content is concise but diverse, starting with an introduction to displays, flat panel imagers, and associated backplane technologies, followed by design specifications and considerations addressing compensation and driving schemes. Here we introduce hybrid voltage-current programming, enhanced-settling current programming, and charge-based driving schemes for high-resolution pixelated architectures.

Although the current mode active matrix provides an intrinsic immunity to mismatches and differential aging, the long settling time at low current levels and large parasitic capacitance is a lingering issue. As explained in Chapter 2, the major source of the settling time in current programming is the large parasitic capacitance. Although using small switch transistors can reduce the parasitic capacitance to some extent [17], the optimized settling time still cannot fit the programming time required for most applications. In addition, the acceleration techniques cannot improve the settling time significantly, particularly if low mobility technologies are used. As a result, driving schemes are required that can reduce the effect of parasitic capacitance based on localized current sources or external driver assistance. This chapter reviews the local current source, current feedback mechanism, and positive feedback described in [98] and [99].

Localized current source

This technique is more useful for compensating for a threshold voltage shift under bias stress and does not work well for process variation. However, it can be used in conjunction with external calibration techniques described in Chapter 6. The idea is to develop the current sources for each pixel locally and therefore eliminate the parasitic capacitance altogether. Our studies show that most TFTs including a-Si:H TFTs are stable if they are under bias stress for a fraction of frame time. Figure 4.1 shows the results of stressing a TFT under 6.5 µA for different stress time during 16 ms frame time. As it can be seen, the output current of the TFT is stable over time even at 500 µs stress time. A local current source based on the short-term stability of the TFTs is demonstrated in Figure 4.2. Here, TLCS converts the voltage stored on its gate to a current. The current in turn adjusts the source voltage of the drive TFT to allow the entire current to pass through the drive TFT. After the programming is finished, the gate voltage of TLCS turns to a reset voltage and so TLCS stays OFF for the rest of the frame time. Figure 4.3 demonstrates the compensation performance of the local current source driving scheme. Here, the threshold voltage of T1 is modified in the simulations and its effect is captured on voltage created at node B and the output current of T1.

Despite the spatial and temporal non-uniformities associated with the TFT, implementation of stable and uniform backplanes in which the TFTs provide analog functions is described in detail with examples. The development of stable driving schemes for different applications is a critical step toward the realization of reliable and practical imagers and displays. In addition to high stability, the implementation cost, power consumption, and additive noise must be mitigated. To maximize the performance of various applications, different solutions are required since the specifications vary substantially. Thus, a set of driving schemes that can cover a wide range of intended applications for TFT backplanes is recommended.

Although the current mode active matrix has an intrinsic immunity to mismatches and differential aging, the long settling time at low current levels and large parasitic capacitance is a lingering issue, particularly for large-area applications. Consequently, a current-biased voltage-programmed (CBVP) pixel circuit that benefits from the high immunity of current programming yet has a fast settling time, low implementation cost, and low power consumption is proposed. In particular, the CBVP driving scheme is adequate for technologies that are prone to mobility as well as VT variations. A 16 × 12 sensor array is fabricated with a CBVP pixel circuit that demonstrates a low noise. The array uses an operational trans-resistance amplifier (OTRA) as the readout circuitry. This enables a faster readout process and therefore real-time operation. In addition, and unlike the hybrid PPS-APS driving schemes, a gain-boosting technique based on a MIS capacitor is developed that can improve the input dynamic range from extremely low to high input signal intensities.

We are witnessing a new generation of applications of thin film transistors (TFTs) for flat-panel imaging [1, 2, 3] and displays [4, 5, 6]. Unlike the active matrix liquid crystal display (AMLCD) where the TFT acts as a simple switch [7], new application areas are emerging, placing demands on the TFT to provide analog functions including managing instability arising from material disorder [3, 6].

In the following sections, we briefly describe the application platforms we have considered in this book, namely flat-panel displays and imaging, along with a summary of performance characteristics of the key TFT technologies used, or being considered, by the large-area electronics industry. While the circuit architectures reported here use examples based on amorphous silicon technology, they are easily adaptable to a broad range of materials families and applications with different specifications.

Organic light emitting diode displays

OLEDs have demonstrated promising features to provide high-resolution, potentially low-cost, and wide-viewing angle displays. More importantly, OLEDs require a small current to emit light along with a very low operating voltage (3–10 V), leading to very power efficient light emitting devices [4–6].

OLEDs are fabricated either by organic (small molecule) or polymeric (long molecule) materials. Small molecule OLEDs are produced by an evaporation technique in a high vacuum environment [8], whereas, polymeric OLEDs are fabricated by spin-coating or inkjet printing [9]. However, the efficiency of small molecule OLEDs is much higher than that of polymeric OLEDs.

For some applications such as high-resolution AMOLED displays for TVs and monitors, as well as for highly sensitive imaging modalities such as radiography and radiotherapy, the backplane should compensate for all the effects caused by the aging or mismatches to achieve the intended accuracy (e.g. less than 0.5% differential aging for a TV screen). While the entire proposed driving scheme compensates only for the static effect of VT-shift (i.e. drop in the pixel current/gain), the transient effects such as charge injection and clock feed-through can cause up to 10% error in the pixel characteristics. To solve this issue, we introduce a calibration technique capable of controlling the transient effects as well as the static effect of the VT-shift (mismatches) [108, 112, 113]. Moreover, a hybrid approach is introduced that takes advantage of both calibration technique and in-pixel compensation.

Time-dependent charge injection and clock feed-through

To compensate for the VT-shift/mismatch, the compensation techniques [64, 67] lead to a modification in the gate voltage of the drive TFT to provide a constant overdrive voltage. However, as a consequence of this change in the gate voltage, clock feed-through and charge injection associated with the parasitic capacitances change over time. Since the storage capacitor cannot be large due to the mandated frame time and aperture ratio, the parasitic capacitances stemming from the overlap of the gate over the drain and source become comparable. Moreover, the threshold voltage of the switch TFTs decreases since they are under negative bias stress during most of the frame time [58]. Consequently, the charge profile of their channels changes for a given programming voltage inducing a time-dependent error.

This chapter presents accelerated programming/resetting of active pixel circuits based on bias currents presented in [87]. The settling time in current programming depends strongly on the VT of the drive transistor and initial line voltage (V0). Figure 3.1 shows the settling time of the pixel circuit depicted in Figure 2.5(a) as a function of the initial voltage. It is evident that the settling time changes as the initial voltage changes. As a result, since the voltage of the previous pixel remains on the data line, the programming of the new pixel is affected. Pre-charging the data lines to a specific voltage can control the effect of the initial voltage, but this can increase the power consumption considerably. Moreover, initial voltage is a function of the VT. Thus, the settling time cannot be managed by a fixed pre-charging voltage, because the value of VT is varying.

Thus, a dynamic line pre-charging scheme, coupled with a large current, is required to improve the settling time. To develop this driving scheme, a fix current is required to program the pixels so that the initial voltage becomes independent of the pixel content. Also, in-pixel current reduction/division is used to adjust the pixel current accordingly. This driving scheme is called the current-biased voltage-programmed (CBVP) scheme [86, 87].

We saw in Chapter 1 that technologies such as poly-Si, a-Si:H, and organic semiconductors are available for the fabrication of pixel circuits. Figure 2.1 demonstrates the three most used TFT structures. Since the bi-layer staggered bottom-gate structure requires fewer mask sets and processing steps, it is highly adopted in industrial scaled a-Si:H fabrication. However, this structure is prone to a higher leakage current, since the back-side of the a-Si:H layer is damaged during the process. An alternative solution to this structure is tri-layer structure in which an etch stopper layer is used to preserve the a-Si:H layer. However, tri-layer structure has more mask layers and process steps compared to bi-layer structure which makes the industry reluctant to adopt it. For poly-Si TFTs, the coplanar top-gate structure is the most common structure. This structure enables self-alignment, resulting in smaller design rules and TFT sizes.

Temporal and spatial non-uniformity

Each of these fabrication technologies is associated with drawbacks for circuit design. However, the key challenge in using the available technologies is the temporal or spatial non-uniformity. In a-Si:H and oxide technologies, the threshold voltage of the TFTs tends to shift (VT-shift) under prolonged bias stress condition (denoted in Figure 2.2). Considering that each pixel in most applications experiences different biasing conditions, the VT-shift will increase the non-uniformity across the panel over time. This phenomenon occurs due to charge trapping and/or defect state creation [58, 59]. The VT-shift has been modeled under different conditions including constant voltage [58, 59], constant current [60], and pulsed stress conditions [61, 62]. Depending on different applications, one of these models can be applied to extract the aging of the pixel. However, in the applications that TFT is under a constant current stress, the VT-shift is severe [60] and unlike the TFT under constant voltage stress, the VT-shift tends to increase forever.