Accelerating Real-Time Network Analytics with Log-Annamalai Negative Binomial Distribution on FPGAs

High-speed network analytics, critical for anomaly detection, traffic shaping, and quality-of-service (QoS) management, demands ultra-low latency probabilistic modeling. Traditional methods for computing the Negative Binomial Distribution (NBD) PMF, often used to model events like packet loss or queue occupancy, suffer from severe numerical instability (overflow/underflow) and high computational latency when dealing with large parameters in hardware. This paper proposes and evaluates an FPGA-based implementation of the Log-Annamalai framework for the NBD. By transforming the complex combinatorial coefficients into a numerically stable sum of logarithms, our approach enables deterministic, single-cycle update latency, significantly reducing resource consumption and eliminating common arithmetic pitfalls. It demonstrates the architecture's suitability for real-time applications such as proactive congestion control and high-frequency anomaly detection in modern network infrastructures.