Chatgpt-Aided-veRIPY (CARIPY): A Generative AI Assisted HLS Tool for Unrolled and Pipelined Hardware Generation

The potential of generative AI (GenAI) in hardware design has attracted growing attention for its ability to translate high-level descriptions into implementation-ready designs. However, directly relying on GenAI to produce Hardware Description Language (HDL) code often results in unstable or non-synthesizable outputs, limiting its practicality in FPGA and hardware development. To address this challenge, this work presents a unified GenAI-VeriPy framework that leverages GenAI’s capability in Python code generation for high-level translation, integrated with VeriPy, a stable Python-based High-Level Synthesis (HLS) backend ensuring reproducible and reliable hardware design. Within this framework, users describe designs in Python and provide concise natural-language instructions through a popular GenAI, ChatGPT. The system reformulates the input into VeriPy-compatible Python, which is synthesised into efficient Verilog. This combined tool, termed ChatGPT-aided-veRIPY (CARIPY), supports pipelined and unrolled architectures, automatic testbench generation, performance and resource estimation, and an extensible hardware library. The framework reduces the learning curve, accelerates prototyping, minimises design errors, and improves generation stability. The generated hardware achieves comparable performance and resource efficiency to VeriPy while significantly shortening input code length. By combining GenAI’s accessibility with VeriPy’s robustness, the framework bridges the gap between software-level design and FPGA hardware implementation for SDR and related applications.