Overview

Over the past several decades, CMOS (complementary metal–oxide–semiconductor) scaling has come to be associated with dramatic and simultaneous improvements in functionality, performance, and energy efficiency. In particular, although the actual historical trends did not uniformly follow a single type of scaling, there was a relatively long period of “Dennard scaling” [1] during which the quadratic (with scale factor) improvements in transistor density were accompanied by a quadratic reduction in power per gate despite a linear increase in switching frequency. All of this was achieved by scaling the operating (i.e., supply) voltage of the circuitry linearly along with the lithographic dimensions of the transistor. Ideally, this would result in constant power consumption per unit chip area, making it relatively easy for chip architects and designers to exploit the increased transistor density with a fixed chip area (and hence power) to cram more functionality into a single die.

Unfortunately, however, as Dennard himself predicted, because of the fact that some intrinsic parameters associated with transistor operation – in particular, the thermal voltage kT/q – do not scale along with the lithographic dimensions, this type of scaling came to an end in the early 2000s. Up until that point, because leakage currents (and hence leakage energy) were essentially negligible, the transistor’s threshold voltage had been treated as a scaling parameter that could be reduced with no significant consequence. However, since leakage current depends exponentially on the threshold voltage, this type of scaling indeed eventually came to a halt.