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Single Wafer Rapid Thermal Multiprocessing

Published online by Cambridge University Press:  25 February 2011

Krishna C. Saraswat ,
Mehrdad M. Moslehi ,
David D. Grossman ,
Sam Wood ,
Peter Wright  and
Len Booth
Krishna C. Saraswat
Affiliation:
Center for Integrated Systems, Stanford University, Stanford, CA, 94305
Mehrdad M. Moslehi
Affiliation:
Currently at Texas Instruments, Dallas
David D. Grossman
Affiliation:
SRC/CIS visitor at Stanford, on leave from IBM Research Ctr., Yorktown Heights, New York
Sam Wood
Affiliation:
Center for Integrated Systems, Stanford University, Stanford, CA, 94305
Peter Wright
Affiliation:
Center for Integrated Systems, Stanford University, Stanford, CA, 94305
Len Booth
Affiliation:
Center for Integrated Systems, Stanford University, Stanford, CA, 94305
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Abstract

Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. We propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. In this paper we describe the development of a novel single wafer Rapid Thermal Multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 146: Symposium B – Rapid Thermal Annealing/Chemical Vapor Deposition and Integrated Processing , 1989 , 3
Copyright
Copyright © Materials Research Society 1989

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References

REFERENCES

[1] Moslehi, M. M., Shatas, S. C., and Saraswat, K. C., “Rapid thermal oxidation and nitridation of silicon,” The Fifth Intl. Symp. on Silicon Materials Sci. and Technol., ECS Proc. vol. 86–4, pp. 379–397, 1986.Google Scholar
[2] Moslehi, M. M., Wright, P., and Saraswat, K. C., “Submicron IGFET Fabrication by Rapid Thermal Processing“, Extended abstract, 45th Annual Device Research Conference, IEEE Electron Devices Society, June 1987, p. IIIB-1.Google Scholar
[3] Moslehi, M.M., Shatas, S.C., Saraswat, K.C. and Meindl, J.D., “Interfacial and Breakdown Characteristics of MOS Devices with Rapidly Grown Ultrathin SiO2 Gate Insulators”, IEEE Trans Electron Dev., Vol. ED–34, No. 6, pp. 1407–1410, June 1987.CrossRefGoogle Scholar
[4] Moslehi, M. M., “Rapid thermal/plasma processing for in-situ dielectric engineering (Invited),” Proc. Mat. Res. Soc. on Rapid Thermal Processing of Electronic Materials, 1987.Google Scholar
[5] Moslehi, M. M., Fu, C.Y., Sigmon, T. W., and Saraswat, K. C., “Low-temperature direct nitridation of silicon in nitrogen plasma generated by microwave discharge,” J. Appl. Phys., vol. 58, no. 6, pp. 2416–2419, 1985.Google Scholar
[6] Wright, P. J., Moslehi, M. M., and Saraswat, K. C., “Electrical Characteristics and Irradiation Sensitivity of IGFETs with Rapidly Grown Ultrathin Gate Dielectrics”, 46th Annual Device Research Conference, The IEEE Electron Devices Society, June 1988, Boulder, Colorado.Google Scholar
[7] Wright, P., Kermani, A. and Saraswat, K. C., “Improved MOS Transistor Properties by Annealing Reoxidized Nitroxides,” IEEE Electron Devices Letters, (To be published).Google Scholar
[8] Wright, P., Kermani, A. and Saraswat, K. C., “Nitridation and Post-Nitridation Anneals of Si02 for Ultrathin Dielectrics,” IEEE Transactions on Electron Devices, (To be published).Google Scholar
[9] Moslehi, M. M., Wong, M., Saraswat, K. C., and Shatas, S. C., “In-situ MOS gate engineering in a novel rapid thermal/plasma multiprocessing reactor,” 1987 Syrup. on VLSI Technol., (Japan) 1987.Google Scholar
[10] Moslehi, M. M., and Saraswat, K. C., “Formation of MOS Gates by Rapid Ther-mal/Microwave Remote-Plasma Multiprocessing”, IEEE Electron Device Letters, Vol. EDL–8, September, 1987, pp. 421–424.Google Scholar
[11] Wong, M. and Saraswat, K. C., “Direct Tungsten on Silicon Dioxide formed by RF Plasma Enhanced Chemical Vapor Deposition,” IEEE Electron Device Letters, Vol. EDL–9, No. 11, November 1988, pp. 582–584.CrossRefGoogle Scholar
[12] Gibbons, J. F., Gronet, C. M. and Williams, K. E., “Limited Reaction Processing: Silicon Epitaxy,” Appl. Phys. Lett., Vol. 47, pp. 721–723, 1985.CrossRefGoogle Scholar
[13] Sturm, J. C., Gronet, C. M. and Gibbons, J. F., “Limited Reaction Processing: In-situmetal-oxide-semiconductor capacitors,” IEEE Electron Device Lett., Vol. EDL–7, No. 5, pp. 282–284, 1986.CrossRefGoogle Scholar
[14] King, C. A., Hoyt, J. L., Gronet, C. M., Gibbons, J. F., Scott, M. P., Rosner, S. G., Reid, G., Laderman, S., Nauka, K. and Kamins, T., “Characterization of p-n Si/Ge Heterojunctions Grown by Limited Reaction Processing,” 46th Annual Device Research Conference, The IEEE Electron Devices Society, Boulder, CO, June 1988.Google Scholar
[15] Carey, P. G., Sigmon, T. W., Press, R. L., and Fahlen, T. S., “Ultra-Shallow High Concentration Boron Profiles for CMOS Processing”, IEEE Electron Dev. Lett., Vol. EDL–6, pp. 291–293, June 1985.Google Scholar
[16] Carey, P. G., Bezjian, K., and Sigmon, T. W., “A Shallow Junction Submicron PMOS Process Without High Temperature Anneals”, IEEE Electron Dev. Lett., Vol. EDL–9, pp. 542–544, October 1988.Google Scholar
[17] Moslehi, M. M., “Process Uniformity and Slip Dislocation Patterns in Linearly-Ramped-Temperature Transient Rapid Thermal Processing of Silicon”, IEEE Transactions on Manufacturing, (To be published).Google Scholar