Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. We propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. In this paper we describe the development of a novel single wafer Rapid Thermal Multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals.

Multistep, in-situ single wafer processing is being explored as an alternative processing approach to standard batch silicon wafer processing. Advantages and disadvantages of this approach are explored and an evaluation given of the potential for future advanced, low temperature wafer processing. Multistep, single wafer processing offers many advantages for advanced device and IC development but much technology research and equipment development is needed to achieve its potential.

Designs of the advanced integrated circuit devices now require much thinner epitaxial films to achieve superior performance. The capability of depositing thin silicon epitaxial layers which have sharp transition width, well-controlled dopant level, high crystallographic quality, and good growth uniformity across the wafer is essential for high speed bipolar and submicron CMOS technologies. This paper describes a thin silicon epitaxial growth process using a recently developed low pressure CVD silicon epitaxial reactor employing rapid thermal processing with incoherent light source. Crystallographic quality, slip formation, transition width, growth uniformity, and dopant uniformity were investigated using TEM, spreading resistance measurements, SIMS, sheet resistance measurements, and FTIR. The SIMS and spreading resistance measurements revealed that auto-doping effect has been minimized. The transition width can be controlled to 10% of the film thickness while maintaining the growth rate up to 1 μm/min at a deposition temperature in the range of 900 - 1000°C. The growth and dopant uniformities across the wafer as determined by FTIR and Prometrix RS-30 Omnimap are better than 1% and 3% per sigma for epitaxial layer thickness under 2 μm. Initial results on selective epitaxial growth was discussed.

Thin silicon films with dendritic large grains can be obtained by Si+ or P+ implantation and subsequent low temperature annealing of the silicon film. We tried further exposing the films with an excimer laser after the grain growth. As a result, improvement of electronic properties such as high carrier mobility or low resistivity were obtained. By TEM observation, polycrystalline grains with a dendritic structure did not melt after laser annealing and it was found that the improvement of electronic properties were achieved mainly due to the improvement of crystallinity by U-V(Ultra-Violet) reflectance, ESR(Electron Spin Resonance) analysis and TFT characteristics. We are convinced that this advanced laser pulse annealing method is an ideal RTA process in the near future and is expected to be applicable to ULSI processes for inter connects, high density stacked SRAM and for large area electronics on glass such as a contact line sensor or LCD(Liquid Crystal Display).

We have investigated the growth rate and boron doping of Sil-xGex epitaxial films grown by Limited Reaction Processing The growth experiments were carried out at a pressure of 6.0 torr with growth temperatures ranging from 625°C to 1000°C. The growth rate increases rapidly upon the additon of a small germane flow to the dichlorosilane in the reaction-rate-limited growth regime, and can not be explained simply by germanium incorporation. The presence of germane can increase the silicon growth rate by up to a factor of one hundred. Boron doping was also studied at high concentrations of boron in Si and Sil-xGex epitaxial films as a function of diborane flow and growth rate supports a simple kinetic model rather than an equilibrium model.

Electrical properties of thin (12 nm) SiO2 films with and without in-situ deposited poly Si electrodes have been studied. Thin SiO2 films were grown by the rapid thermal oxidation (RTO) process and the poly Si films were deposited by the rapid thermal chemical vapor deposition (RTCVD) technique at 675°C and 800°C. Good electrical properties were observed for SiO2 films with thin in-situ poly Si deposition; the flatband voltage was ∼ -0.86 V, the interface state density was < 2 × 1010/cm2/eV, and breakdown strength was > 10 MV/cm. The properties of RTCVD poly Si were also studied. The grain size was 10-60 rim before anneal and was 50-120 rim after anneal. Voids were found in thin (< 70 nm) RTCVD poly Si films. No difference in either SiO2 properties or poly Si properties was observed for poly Si films deposited at different temperatures.

Rapid thermal chemical vapor deposition (RTCVD) is a processing technique that results from the combination of radiant heating lamps and a CVD chamber. It is the ultimate cold-wall CVD reactor and allows one to clean wafers in-situ and immediately thereafter deposit epitaxial layers. Very thin layers (<100 Å) can be deposited by either gas or lamp power switching. We report here the growth of high quality Si and Si-Ge layers, both intrinsic and in-situ doped, and the in-situ growth of a heterojunction bipolar transistor. These HJBT's show gains as high as 350 and are promising as microwave transistors. RTCVD processing is a production-worthy technology that will play an important role in the manufacture of future heterostructural devices.

Si/SiGe heterostructures offer improved performance for many electronic and optoelectronic Si devices. The expected improvement in device characteristics depends critically on the structural perfection and precise compositional control of the epitaxial layers. This implies a combination of abrupt interfaces, on the order of 10 Å, capability of maintaining high doping levels, in the 1019 cm−3 range, with a similar spatial resolution, and low density of electrically active defects. These requirements are particularly stringent in the case of Ge-rich alloys for which the critical layer thicknesses are below ∼100 Å. The desired characteristics can be obtained by low temperature techniques such as molecular beam epitaxy (MBE) and rapid thermal chemical vapor deposition (RTCVD).

In an effort to extend the performance limits of semiconductors, devices based on heterojunctions rather than homojunctions are being investigated with great interest. Heterojunctions allow certain device design constraints to be relaxed because the charge distribution, electric field, and potential can be tailored extensively, permitting better device structures to be utilized. Silicon technology today enjoys a firm grip on a large portion of the electronics industry due in part to its superior material properties.

Single-Wafer Integrated in-situ Multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn-around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/GexSil-x/Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications.

The deposition of polycrystalline silicon in a rapid thermal processor was studied in the temperature range of 600-1100°C using a mixture of silane and argon at reduced pressures. The amorphous-to-polycrystalline transition temperature was determined by X-ray diffraction and UV-visible spectrophotometry to be between 650 and 700°C. The activation energy of the deposition was found to be approximately 1.5 eV in the temperature range of 600 to 800°C, in reasonable agreement with LPCVD and APCVD results. At 800°C and above, the deposition rate depended only weakly on temperature, as is characteristic of mass-transport-fimited processes. The partial pressure of silane was found to affect the deposition rate in both surface-limited and gas-transport-limited depositions. A UV-visible spectrophotometer was used as a reflectometer to measure the surface roughness of the samples, which in general increased with increasing deposition temperature and film thickness. At the lower deposition temperatures, the surfaces were very smooth, as is characteristic of amorphous-silicon films. Furthermore, the ability to change temperature rapidly appears to allow smoother films to be obtained by initially depositing at lower temperatures, and then ramping to a higher temperature to increase the deposition rate.

The deposition of beta Silicon Carbide unto single crystal silicon (100) wafers using rapid thermal chemical vapor deposition (RTCVD) has been carried out using silane and ethylene as the source gases. Deposition temperatures were varid from 1100°C to 1300°C. Auger analysis revealed the silicon carbide films to be stoichiometric at all temperatures. Infrared spectroscopy data taken between 1200 cm−1 and 60° Cm−1 show the appearance of the longitudinal optical phonon at 974 cm−1 and the transverse optical phonon at 794 cm−1 in samples deposited at 1200°C and above. Stress in the films deposited on the single crystal silicon substrates is seen to go from zero or slightly compressive at 11O0°C to strongly tensile at 1300°C.

Low-pressure chemical vapor deposition of polycrystalline silicon and silicon dioxide in a lampheated cold-wall rapid thermal processor have been investigated. Silicon dioxide films have been deposited by thermal decomposition of tetraethylorthosilicate known as TEOS. The technique can be used for rapid deposition of good quality thick passivation layers at moderate temperatures. Polycrystalline silicon depositions have been accomplished using silane (SiH4) diluted in argon as the reactive gas. Surface roughness and resistivity of the films deposited at temperatures above 700°C are comparable in quality to films deposited in a conventional LPCVD reactor at 610°C. In this temperature range, deposition rates as high as 4000Å/min can be obtained.

Rapid thermal processing chemical vapor deposition was used to grow single and multilaye repitaxial GexSil-x/Si structures on (100)Si substrates using GeH4 and SiH2Cl2 at 900°C and 1000°C with SiH2Cl2:GeH4 ratios of 14:1 to 95:1 at 5 Torr. Misfit dislocation free layers with few threading dislocations were grown for Ge concentrations of up to 13%. Misfit dislocation networks aligned along <110> were formed at the interface of films with higher Ge concentrations. Dislocation loops were also found at the interface. GexSil-x layers grown at 1000°C were highly crystalline, but relaxed. In multi-layer structures, AES depth profiles showed Ge pile-up at the GexSi1-x/Si interface of layers with higher Ge concentrations.

The precursors of Si film in SiH4 low pressure thermal CVD are studied by use of the trench coverage analysis. The cross sectional profile of the film deposited in a trench is simulated by a direct Monte-Carlo method using the composition of the precursors and their sticking probabilities as adjustable parameters. A comparison with the experimental results[1] shows that the trench coverage profiles are well reproduced by the model where two kinds of precursors deposit independently with respective sticking probabilities of almost zero and unity. The former is silane molecule, and the latter is radicals produced by gas phase reactions. The deposition rate due to radicals can be estimated from the comparison. Considering the sticking probability and the SiH4 pyrolysis reactions, it is concluded that H3SiSiH is one of ate dominant film precursors in gas phase reaction products.

Silicon epitaxy plays an important role in improving the performance and reliability of semiconductor devices. The continuous scale-down in device feature size demands a low thermal budget epitaxial technique to maintain the structural integrity of processed devices. In this paper, rapid thermal processing chemical vapor deposition (RTP-CVD) has been used to deposit high quality, thin silicon epitaxial films with superior thickness control. Parameters affecting the quality and rate of epitaxial growth are discussed.

This paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.

Low temperature Si processing techniques have been developed using remote plasma enhanced chemical vapor techniques. The 300° C in situ processes include indirectly excited hydrogen treatments for obtaining reconstructed Si(100) surfaces, Si/Si(100) homoepitaxy, and deposition of poly-Si/oxide/nitride/oxide/Si(100) structures with no capacitance-voltage hysteresis and low interface state density (4×1010cm−2eV−1). While all these processes have been accomplished with the same tool, the success of the in situ hydrogen treatment and the homoepitaxy are sensitive to the past history of the reactor. In particular, they are sensitive to by-products formed during the oxide deposition process. To eliminate these by-products, plasma conditioning of the chamber walls prior to introduction of the silicon wafer from the load lock has been necessary to obtain reproducible results.

The influence of patterned oxide layers on temperature non-uniformity during RTP is studied. It is shown that large temperature non-uniformities (up to 80 °C) can occur during RTP as a consequence of large scale patterns of thick oxides. The dependence of oxide thickness and pattern geometry on temperature non-uniformity over a wafer is studied. A set of simulation programs is developed to calculate the optical characteristics of a wafer inside a chamber and to calculate the time dependent temperature non-uniformities on patterned wafers. The calculated results agree very well with the experimental results. The simulation program was used to define the optimal optical conditions for RTP systems for minimal temperature non-uniformity due to patterned overlayers on Si.

Low temperature silicon epitaxy is critical to novel silicon-based devices requiring hyper-abrupt transitions in doping profiles or heterointerfaces. Epitaxy by Remote Plasma-Enhanced Chemical Vapor Deposition (RPCVD) consists of an in situ remote hydrogen plasma clean of the silicon surface followed by growth of silicon from silane at 220° - 400°C. Reconstruction of the silicon (100) surface from a (1×1) to a (2×1) structure after cleaning at 310°C is observed by RHEED, indicating an atomically clean surface. The removal of carbon and oxygen has been further substantiated by Auger Electron Spectroscopy (AES) and growth on these atomically clean substrates has produced good quality epitaxial films. Using remote hydrogen plasma cleans at lower temperature we report the first observation of third-order silicon surface reconstruction on a Si(100) surface, where two faint fractional order streaks between the sharp integral order streaks are observed. After a short (5 minute), low temperature (300-400 °C) anneal the third order pattern transforms rather quickly to a strong (2×1) reconstruction pattern. The third order pattern can then be restored by following the anneal with a repeat of the lower temperature hydrogen clean. Although the origin of the third order pattern is unclear at this time, we believe it is due to a Si-H complex formation at the silicon surface.