Integration of the III–V channel MISFETs on the Si platform is a potential solution to realize performance improvement and power reduction in the sub-22 nm node and beyond. To take advantage of the high electron mobility of III-Vs, the MIS interfaces of high integrity should be developed. This paper reports how the MIS characteristics vary in response to the changes in the interface composition and structures, and discusses the physics and chemistry behind these observations. We fabricated a wide variety of the high-k/III–V interface structures by employing the state-of-the-art technologies of the epitaxial wafers by MOCVD, surface reconstruction control in the MBE environment, wet/dry surface treatments optimized by utilizing XPS/AES analyses, and deposition of quality dielectrics (Al2O3, HfO2) by ALD and EB evaporation. The MIS characteristics were evaluated in the capacitor and FET structures. The talk will include the following topics: the effects of the cation composition (Al, Ga, In) of the III-V bulk on the MIS characteristics , the importance of the anion control (N, S) at the interface to improve the MIS characteristics, and the surface orientation ((100) vs. (111)) as a new parameter in the III-V MIS device design . This work was carried out in the Nanoelectronics Project supported by NEDO/METI.  T. Yasuda et al., as discussed at 39th IEEE SISC (San Diego, Dec. 2008).