Introduction

Although the event driven simulator allows timing to be included in a simulation, it is extremely difficult to devise a set of tests that would show up all possible timing problems. Such a set of tests would have to analyse the network structure to find where two paths from the same signal converge later in the network. One of these would have to be assigned maximum delay and the other minimum. Such a situation was shown in Fig. 1.1 given that the two inputs were related and is known as reconvergent fan-out. The four-gate not equivalence example has five cases of reconvergent fan-out. A procedure is needed to find unwanted short pulses. It requires that all associated signals have the relevant states, which is why it can be difficult to drive. Having found a potential short pulse, it must be decided whether it matters. At the input of another gate, it does not. At the asynchronous input to a flip-flop, it most certainly does.

The second problem with timing is to be sure that the longest path, often known as the critical path, through a combinational network has been activated in order to ensure that the logic can operate within the design time specified. In particular, with synchronous logic, it is necessary to check that the logic works within the specified clock periods. The naive analysis of the four-gate not equivalence circuit designed earlier indicated the dangers of pattern sensitivity. That analysis was by no means complete (Section 6.4, last paragraph).