Optimizing process- and layout-design in the development
of modern electronic devices is key to achieve required
characteristics.
Coming along with the growing complexity of
device structures, associated effects must be considered in an even
more complex
manner. The use of three-dimensional process-
and device-simulation tools is inevitable. Because of the huge effort
concerning computer resources
from three-dimensional simulations it is of big interest to
enable efficient ways for optimization,
as early as possible in process flow.
Hence this work shows, how it was possible, to optimize a
high-voltage PMOS transistor before starting a complex three-dimensional
device simulation.