In this paper both the substrate doping concentration and single crystal silicon orientation are considered when dielectrics are grown on silicon in a nitrous oxide environment. Our initial preliminary findings show that for heavily doped subtrates thicker layers of dielectric result compared to their lower doped counterparts. Furthermore we find a crossover point of temperature for growth rate for <111> compared to <100>. We believe that the different growth rates are attributable to nitrogen build up at the dielectric interface.

Polycrystalline silicon films have been amorphized by implantation with 100keV Ga ions of doses 0.3 and 6×1015cm−2. These films were subsequently recrystallized using either a furnace for longer times lower temperature (∼30 mins, 600° C) or rapid thermal processing (RTP) for shorter times higher temperatures ( ≤ 30 sec, 800° C, 900° C) in an endeavour to suppress any long range movement of the Ga during the anneal phase. It is found that for both the furnace and RTP for temperatures ≤ 800°C no significant movement is observed and that the lower temperature anneal for the highest dose produces the highest electrical conductivity. By contrast however, annealing at 900° C, even though the initial conductivity is higher than for any other anneal we observe a significant reduction with time and extremely rapid movement of the dopant species throughout the original poly layer. An initial rationale for this behaviour is proposed in terms of a liquid phase transformation during annealing.

High doses: 1, 3 and 6×1015/cm2 of Ga71+ ions were implanted into <100> silicon at 100keV and annealed in the temperature regime of 550-675° C for seconds to tens of seconds. Two different annealing rigs were used; however the physical and electrical results obtained from each provided remarkably similar results.

We have observed a regrowth rate/dose dependency through both our physical and electrical measurements that provide surprisingly good correlation. We also note that for the highest dose complete solid phase epitaxial regrowth is inhibited, and for temperatures as low as 640°C and times as short as 9sec. onset of movement of the gallium toward the surface is observed. We also show that extremely high free carrier concentrations of gallium can be obtained under the correct anneal conditions.

Undoped polycrystalline silicon (poly-Si) films obtained by low pressure chemical vapour deposition (LPCVD) techniques have previously been demonstrated to align epitaxially with respect to the underlying (100) silicon substrate in the 1000-1100°C temperature regime. However the alignment rate at temperatures in excess of 1100°C is too rapid to be obtained by conventional furnace processing. Rapid Thermal Processing (RTP) offers an excellent technique of attaining this temperature in the requisite time and in this paper we report on the results of a study in which RTP has been used. Our results show an activation energy of ∼4.5eV, and that the growth rate constant is dramatically enhanced, without any alignment delay in the initial heat treatment phase, which is contrary to previous findings.

This paper presents the results obtained from a comparative study of ion implanted Gallium (Ga) into (100), n type Silicon. A comparison is made between long time (≥ 30 mins) furnace annealed and Rapid Thermally Processed (RTP), 100keV implants of 1 and 3×10l5/cm2 doses of Ga. The results show that for RTP an extremely high substitutional concentration of Gallium, in excess of 3×1020/cm3 can be obtained with approximately 100% electrical activation, resulting in highly conductive very shallow p type layers.

Single crystal silicon has been implanted with low energy (20 keV) phosphorus ions and a comparison made of furnace annealing (which produces excellent solar cells) and rapid annealing using a radiant incoherent light source. The light source is used to anneal and activate implanted layers in the isothermal mode on a time scale of the order of seconds compared with the much longer furnace annealing times of several hours.

Initial results using the incoherent light source show a high dark current and inferior photoresponse. However a subsequent thermal treatment at 600°C for 10–15 minutes shows that the resultant photoresponse can approach that of the longer time furnace anneal. Transmission electron microscopy shows the formation of large voids (20–100 nm) after the initial annealing phase. These reduce in size after furnace annealing. This photoresponse may be related to this void formation.

An integral part of very large scale integrated (VLSI) circuits is the multilayer structures for electrical interconnection and insulation. Many conducting materials are used for interconnection including polysilicon, silicon, silicides, polycides and metals. An important point in considering these materials is the interconnection between them and the corresponding characterization of the interface by way of the specific contact resistance, which directly affects the interfacial contact resistance.

For a planar ohmic contact formed between a metal and any layer with a much larger sheet resistance (for example single crystal silicon) a technique based on the transmission line model provides a method of characterizing these contacts. However, for planar contacts between layers with comparable sheet resistivities for example polysilicon to single crystal silicon this technique must be modified. In this paper we review the transmission line approach used to obtain the specific contact resistance between such layers and provide initial results of measurements made on the poly to single crystal interface. We also present a series of test structures, currently under fabrication that will provide more detailed experimental data.

We present results which highlight applications of a continuous wave incoherent light source in the processing of semiconductor devices. In particular, damage removal and activation of ion implanted gallium arsenide is demonstrated for both capless and capped annealing of low dose implants at temperatures of > 800°C for times < 10 s. For gallium arsenide FET applications, we demonstrate that it is possible to simultaneously carry out activation, contacting and interconnection steps by utilizing thermomigration processes which are not available with conventional furnace processing. In silicon we demonstrate that shallow multi layer bipolar structures can be successfully fabricated with anneal cycles that lead to supersaturation effects and negligible diffusion.

Rutherford backscattering, Van der Pauw and TEM measurements were used to characterise the annealing behaviour of antimony implanted LPCVD polysilicon. High electrical activity without dopant redistribution was obtained for 600°C annealing of 1 × 1015 cm−2 and 3×1015 cm−2 antimony implanted samples. Subsequent annealing at temperatures ≥900° C resulted in considerable grain-boundary-assisted redistribution of antimony within the polycrystalline layers and associated changes in sheet resistance. Our results suggest that the sheet resistance of the films is controlled by dopant segregation at grain boundaries and the fraction of antimony distributed on active sites within individual grains.

simple radiant light source has been employed to rapidly anneal ion implanted silicon structures at temperatures >1000° C for times of the order of 1–200 sec. Rutherford backscattering and channeling analysis indicated good crystalline lattice recovery and the formation of metastable solid solutions of Sb in Si without observable diffusion broadening of the implanted profile. Diode arrays have been successfully annealed using the technique, with no observable deterioration of the surrounding oxide mask.