In order to alleviate the test generation complexity, one needs to model the actual defects that may occur in a chip with fault models at higher levels of abstraction. This process of fault modeling considerably reduces the burden of testing because it obviates the need for deriving tests for each possible defect. This is made possible by the fact that many physical defects map to a single fault at the higher level. This, in general, also makes the fault model more independent of the technology.

We begin this chapter with a description of the various levels of abstraction at which fault modeling is traditionally done. These levels are: behavioral, functional, structural, switch-level and geometric.

We present various fault models at the different levels of the design hierarchy and discuss their advantages and disadvantages. We illustrate the working of these fault models with many examples.

There is currently a lot of interest in verifying not only that the logical behavior of the circuit is correct, but that its temporal behavior is also correct. Problems in the temporal behavior of a circuit are modeled through delay faults. We discuss the main delay fault models.

We discuss a popular fault modeling method called inductive fault analysis next. It uses statistical data from the fabrication process to generate physical defects and extract circuit-level faults from them. It then classifies the circuit-level faults based on how likely they are to occur.