In this chapter, we first discuss the challenges we face in test generation and fault simulation of sequential circuits. We then discuss classification of the fault simulation methods, test generation methods, and different types of faults.

Next, we discuss how the fault list can be collapsed in a sequential circuit. We show that the concept of fault dominance is only selectively applicable to such circuits.

Under fault simulation, we discuss a method which combines the best of different conventional fault simulation methods and tries to avoid their pitfalls.

Under test generation, we discuss three types of methods: those which derive tests from the state table, those which assume full reset capability, and those which do not assume any reset capability. We show how test generation techniques obtained for synchronous sequential circuits can be extended to asynchronous sequential circuits. Then we discuss methods for compacting the test set.

Classification of sequential ATPG methods and faults

Sequential automatic test pattern generation (ATPG) is a difficult problem. The many challenges we face in this area include reduction in the time and memory required to generate the tests, reduction in the number of cycles needed to apply the tests to the circuit, and obtaining a high fault coverage. Adding to the complexity of this problem is that, unlike a combinational circuit where an untestable fault is also redundant, an untestable fault is not necessarily redundant in a sequential circuit.