In this chapter, we discuss how CMOS circuits can be tested under various fault models, such as stuck-at, stuck-open and stuck-on. We consider both dynamic and static CMOS circuits. We present test generation techniques based on the gate-level model of CMOS circuits, as well as the switch-level implementation.

Under dynamic CMOS circuits, we look at two popular techniques: domino CMOS and differential cascode voltage switch (DCVS) logic. We consider both single and multiple fault testability of domino CMOS circuits. For DCVS circuits, we also present an error-checker based scheme which facilitates testing.

Under static CMOS circuits, we consider both robust and non-robust test generation. A robust test is one which is not invalidated by arbitrary delays and timing skews. We first show how test invalidation can occur. We then discuss fault collapsing techniques and test generation techniques at the gate level and switch level.

Finally, we show how robustly testable static CMOS designs can be obtained.

Testing of dynamic CMOS circuits

Dynamic CMOS circuits form an important class of CMOS circuits. A dynamic CMOS circuit is distinguished from a static CMOS circuit by the fact that each dynamic CMOS gate is fed by a clock which determines whether it operates in the precharge phase or the evaluation phase. There are two basic types of dynamic CMOS circuits: domino CMOS (Krambeck et al., 1982) and DCVS logic (Heller et al., 1984).