17 results
Foreword
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- By Jean-Pierre Colinge, CEA-LETI, France
- Farzan Jazaeri, École Polytechnique Fédérale de Lausanne, Jean-Michel Sallese, École Polytechnique Fédérale de Lausanne
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- Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors
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- 24 February 2018
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- 01 March 2018, pp xi-xii
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7 - Nanowire Transistor Circuits
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 221-248
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Summary
CMOS circuits
Nanowire FETs can be used in the same fashion as any other type of MOSFET to construct the logic gates that are the building blocks for data processors and control circuits, as well as memory cells of various types such as static random access memory (SRAM), flash memory, and so on. The topology of nanowire transistors makes them particularly suitable for making array-like circuits such as crossbar nanowire circuits and nanoscale application-specific integrated circuits. Nanowire FETs can even be used as photodetectors [1]. Last but not least, nanowire transistor-based sensors can also be combined with CMOS electronics to deliver powerful chemical or biomedical analytical devices.
Nanowire transistors can be used as single devices. They can also be used in serial or parallel combinations. Figure 7.1 shows horizontal nanowire transistors in a parallel configuration; using this architecture a high current drive with a small layout footprint can be achieved [2]. Vertical nanowire transistors lend themselves quite naturally to the formation of NAND-based architectures as shown in Fig. 7.2.
CMOS logic
Techniques for the design and optimization of nanowire circuits are still in their infancy. Key performance indicators (KPIs) include ON/OFF currents, effective current and effective gate capacitance, CV/I, integration density, and other performance measures normally associated with CMOS transistors. Key process and layout parameters include number of nanowires per transistor, footprint, nanowire diameter, and other process-related parameters such as gate length, gate over-underlap length and source/drain (S/D) region length. One particular study indicates that through design optimization, the total capacitance and parasitic resistance of typical nanowire CMOS gates can be reduced by over 80% compared to nanowire designs without optimized process parameters. Significant improvements are achieved through the reduction of the source/drain extension length, gate overlap, and nanowire diameter. Optimization of the device parameters can also achieve an improvement of over 90% reduction in delay and power consumption at the circuit level [3].
With the decrease of both device dimensions and supply voltage, variability has become an important issue in integrated circuit fabrication. Device parameters such as threshold voltage, drain-induced barrier lowering (DIBL), and ON and OFF currents exhibit statistical variations. The origins of these variations are multiple and include gate line edge roughness (LER), random doping fluctuations (RDF), nanowire diameter variations, and/or nanowire surface roughness.
5 - Nanowire Electronic Structure
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 107-166
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Summary
Overview
The electronic structure of a semiconductor nanowire can vary substantially with respect to bulk material properties due to orientation, diameter, strain, quantum confinement, and surface effects. Before introducing the electronic structure of nanowires, the crystal structures of common group IV and III-V binary compounds are introduced. Semiconductor nanowires, even for diameters of a few nanometers, can retain the bonding characteristic of their bulk crystalline forms. This permits classification of nanowires by the crystal orientation aligned to the nanowire long, axial, or “growth” axis. To determine electronic structures of materials generally requires a combination of experimental and theoretical approaches in a fruitful collaboration whereby the strengths of several methods are used to complement one another. Elementary analysis of band structures is considered in relation to the observed properties of materials leading to their categorization as insulators, semiconductors, semimetals, and metals. These basic material categories are the fundamental building blocks for nanoelectronic devices. A brief discussion of experimental and theoretical methods for the determination of electronic properties is given to provide background on the state-of-the-art for electronic structure characterization and calculations. The electronic band structures of common bulk semiconductors are presented for reference. Atomic scale models for nanowires oriented along different crystal directions are introduced with the relationship between confinement normal to a nanowire's long axis and electronic structure expressed in terms of band folding. Representative electronic band structures are then introduced for different nanowire systems based on diameter and orientation to highlight the key effects of reduced dimensionality on electronic structure.
Semiconductor crystal structures: group IV and III-V materials
Group IV bonding and the diamond crystal structure
Silicon crystallizes in a cubic crystal structure that has the same symmetry as the diamond form of carbon. This structure is referred to as the diamond cubic crystal structure or sometimes more colloquially as the “diamond lattice.” The local bonding characteristic of the diamond crystal structure is largely retained when nanowires are patterned from crystalline silicon or grown from bottom-up processes such as those described in Chapter 3. In the diamond structure, each atom is tetrahedrally bonded to four nearest neighbor atoms. Many materials can also exist in amorphous form whereby the long-range order of a crystal is lost.
4 - Quantum Mechanics in One Dimension
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 81-106
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Summary
Overview
Solid-state physics is primarily concerned with the quantum mechanics of bulk materials and surfaces. Molecular physics and quantum chemistry are similarly the application of quantum mechanics to molecular problems. Bulk materials may be described as three-dimensional objects, and their spatial dimensions have a significant influence on the allowed solutions for quantum mechanical energy states or levels. These quantum mechanical levels in three dimensions give rise to electronic band structures which are commonly used to define a material as a metal, insulator, or semiconductor. Energy bands are formed from quantum mechanical states that are nearly continuous in energy. If the states that comprise a band are only partially filled with electrons, a metal is formed. For a fully occupied band separated by a relatively small energy gap, a semiconductor is the result. If the energy gap between a filled band and an empty band is large, the material is described as an insulator. Molecules are zero-dimensional objects with vanishing of the wave function in all three spatial directions and the bound electrons do not propagate. This gives rise to a discrete energy spectrum that is characteristic of molecules; the spacing between energy levels is large and there is no corresponding band picture of the electronic spectrum.
Modern epitaxial growth, lithography, chemical synthesis, self-assembly, and scanning probe techniques allow for the fabrication of material systems that are intermediate in dimensionality to solids and molecules. When electrons or holes are confined in a single direction and are free to propagate in two directions, a two-dimensional electron or hole gas (2DEG or 2DHG) is formed. If electrons or holes are confined in two dimensions and electrons or holes are free to move in a single spatial direction, a nanowire or one-dimensional (1D) structure is formed. In the following, quantum mechanics is introduced with a focus on the physics of 1D or nanowire structures with emphasis on the concepts relevant to engineering transistor structures on the nanoscale.
Survey of quantum mechanics in 1D
Quantum mechanics relies on the use of state vectors to describe a physical system and operators are used to determine physical properties that are measurable. In quantum mechanics, the systems that are subject to measurement are of the same scale as the smallest experimental probes that can be devised.
Frontmatter
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp i-iv
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Index
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 249-254
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Contents
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp vii-x
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1 - Introduction
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 1-17
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Summary
The history of electronics spans over more than a century. A key milestone in the history of electronics was the invention of the telephone in 1876 and patents for the device were filed independently by Elisha Gray and Alexander Graham Bell on 14 February that same year. Bell filed first, and thus the patent was granted to him. This timely, or untimely for Gray, coincidence has become a textbook example for teaching the importance of intellectual property law in engineering schools across the globe.
Years later, the first radio broadcast took place in 1910 and is credited to the De Forest Radio Laboratory, New York. Lee De Forest, inventor of the electron vacuum tube, arranged the world's first radio broadcast featuring legendary tenor Enrico Caruso along with other stars of the New York Metropolitan Opera to several receiving locations within the city. Experimental television broadcasts can be traced back to 1928, but practical TV sets and regular broadcasts date back to shortly after the Second World War.
During this initial phase of development, electronics was based on vacuum tubes and electromechanical devices. The first transistor was invented at Bell Labs by William Shockley, John Bardeen, and Walter Brattain in 1947 and they used a structure named a point-contact transistor. Two gold contacts acted as emitter and collector contacts on a piece of germanium. William Shockley made and patented the first bipolar junction transistor in the following year, 1948. It is worth noting that the point-contact transistor was independently invented by German physicists Herbert Mataré and Heinrich Welker of the Compagnie des Freins et Signaux, a Westinghouse subsidiary located in Paris [1].
The first patent for a metal-oxide-semiconductor field-effect transistor (MOSFET) was filed by Julius Edgar Lilienfeld in Canada and in the USA during 1925 and 1928, respectively [2,3]. The semiconductor material used in the patent was copper sulfide and the gate insulator was alumina. However, a working device was never successfully fabricated or published at that time. The first functional MOSFET was made by Dawon Kang and John Atalla in 1959 and patented later in 1963 [4]. The successful field-effect operation was enabled by the use of silicon and silicon dioxide for the metal-oxide-semiconductor (MOS) stack.
3 - Synthesis and Fabrication of Semiconductor Nanowires
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 54-80
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Summary
Semiconductor nanowires can be fabricated using a variety of techniques. Techniques based on the semiconductor industry legacy of using lithography patterning and material removal methods to etch semiconductor layers into nanowires are called “top-down” fabrication techniques. A typical example is the patterning of photoresist lines on top of a silicon-on-insulator layer followed by the removal of excess silicon using a plasma etch tool in order to create silicon nanowires. Another example is the patterning of an array of “dots” on a silicon substrate and the use of plasma etching to fabricate vertical silicon columns. Techniques based on the direct epitaxial growth of a nanowire from a seeding substrate without using material removal techniques are called “bottom-up” growth techniques. The classical example is the vapor–liquid–solid (VLS) growth of silicon nanowires on a silicon substrate using gold eutectic droplets [1,2].
Top-down fabrication techniques
In this section, the more common “top-down” fabrication techniques are described. They are typically based on process steps used following the semiconductor industry legacy by combining patterning using lithography and material removal using etching tools allowing the shaping of thin semiconductor films into nanowire structures.
Horizontal nanowires
Semiconductor nanowires can be fabricated using either semiconductor-on-insulator wafers or bulk semiconductor wafers. In the case of silicon, nanowires can be made using a silicon-on-insulator (SOI) wafer. The silicon film thickness can be trimmed down to the desired value using oxidation and wet oxide strip in a buffered hydrofluoric acid (HF) solution [3,4]. The lateral dimensions of the nanowire are usually defined using e-beam lithography permitting patterning of very narrow lines [5,6,7]. Other techniques, such as the use of block copolymer self-assembly, can be used to define narrow polymer parallel lines and use them as a template for pattern transfer onto a semiconductor. Directed self-assembly of block copolymers is capable of achieving high-density patterning with critical dimensions approaching 5 nm. High-density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer has been demonstrated. The wires are formed with a pitch of 42 nm resulting in dense arrays (5 × 106 wires/cm) of unidirectional and isolated parallel silicon nanowires on an insulator substrate. This technique demonstrated the fabrication of nanowires with critical dimension ranging down to less than 10 nm [8,9].
Preface
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp xi-xiv
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Summary
After the era of bulk planar CMOS, trigate field-effect transistors (FinFETs), and fully depleted silicon-on-insulator (SOI), the semiconductor industry is now moving into the era of nanowire transistors. This book gives a comprehensive overview of the unique properties of nanowire transistors. It covers the basic physics of one-dimensional semiconductors, the electrical properties of nanowire devices, their fabrication, and their application in nanoelectronic circuits.
The book is divided into seven chapters:
Chapter 1: Introduction serves as an introduction to the other chapters. The reader is reminded of the exponential increase in complexity of integrated circuit electronics over the last 50 years, better known as “Moore's law.” Key to this increase has been the reduction in transistor size, which has occurred in a smooth, evolutionary fashion up to the first decade of the twenty-first century. Despite the introduction of technology boosters such as metal silicides, high-κdielectric gate insulators, copper metallization, and strained channels, evolutionary scaling reached a brick wall called “short-channel effects” in the years 2010–2015. Short-channel effects are a fundamental device physics showstopper and prevent proper operation of classical bulk MOSFETs at gate lengths below 20 nm. The only solution to this problem is the adoption of new transistor architectures such as fully depleted silicon-on-insulator (FDSOI) devices [1,2] or trigate/FinFET devices [3]. Ballistic transport of channel carriers, which replaces classical drift-diffusion transport, is also introduced in this chapter.
Chapter 2: Multigate and nanowire transistors first explains the origin of the short-channel effects that preclude the use of bulk MOS transistors for gate lengths smaller than 20 nm. Based on Maxwell's electrostatics equations, this chapter shows how the use of multigate and gate-all-around nanowire transistor architectures will allow one to push the limits of integration to gate lengths down to 5 nm and possibly beyond, provided the diameters of the nanowires are decreased accordingly. In semiconductor nanowire with diameters below approximately 10 nm (this value is temperature dependent and varies from one semiconductor material to another), the coherence length of electrons and holes can become comparable to or larger than the wire cross-sectional dimensions, and one-dimensional (1D) quantum confinement effects become observable. The formation of 1D energy subbands in narrow nanowire transistors gives rise to several effects such as an increase of energy band gap, oscillations of drain current when gate voltage is increased, and oscillations of gate capacitance with gate voltage (quantum capacitance effect).
6 - Charge Transport in Quasi-1d Nanostructures
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 167-220
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Summary
Overview
This chapter introduces how electron and hole currents can be described in nanostructures with emphasis on how quantum mechanical effects arise when treating charge transport in small cross-section semiconductor nanowires. Discussion of the voltage sources that drive electrical behavior alongside the relationship of voltage to current in quantum mechanical systems leads to the property of conductance quantization. An overview of the relationship of charge carriers (electron, hole) scattering to mobility and the relationship to mean free paths is introduced. Transistor channels with length scales below or comparable to the mean free paths for electrons or holes are considered leading to quasi-ballistic transport. In the quasi-ballistic regime only a few scattering events can occur resulting in macroscopic properties such as mobility, diffusion, and drift velocity becoming inapplicable and charge carrier transport is no longer described by classical drift and diffusion mechanisms. The chapter concludes with an introduction to Green's function approaches, which are suitable for describing charge transport in the scattering regimes ranging from purely ballistic, to quasi-ballistic, to ohmic conduction.
Voltage sources
Semi-classical description
Before embarking on a discussion on how to calculate electron and hole currents in nanowire structures, it is useful to consider the physical description of a voltage source. A non-equilibrium condition is required to be built up across the nanowire or “device” region to provide the charge imbalance that gives rise to electric current. To understand how a battery or power supply acts to create such a non-equilibrium condition, the result of a voltage applied by a battery between two disconnected (open circuit) electrodes is examined. Within a battery, electrochemical cells provide a potential difference that results in a deficiency of electrons on the cathode (positive terminal) and an excess of charge on the anode (negative terminal). Figure 6.1 provides a simple depiction of a battery connected to two electrodes shown as metal regions with wires connecting them to a battery or other voltage source. It is assumed the wires are ideal conductors and the electrodes are metallic. Hence in a cathode electrons are pulled away from the metal electrode leaving a net positive charge behind, whereas an excess of negative charge is built on the anode.
2 - Multigate and Nanowire Transistors
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 05 April 2016
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- 21 April 2016, pp 18-53
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Summary
As presented in Chapter 1, the use of a multigate architecture is a technology booster that allows improved electrostatic control of a channel region by the gate electrode, and therefore mitigates short-channel effects. Currently existing multigate architectures for the MOSFET are described, and then compared in terms of short-channel effect control. It is concluded that the gate-all-around structure associated with a nanowire-shaped semiconductor offers the best possible electrostatic control of a channel. Different effects arising from carrier confinement effects in semiconductor nanowires are considered. The chapter concludes with a discussion of novel phenomena arising from quantum confinement, such as the semimetal–semiconductor transition, band folding of the electronic structure in nanowires, and novel devices that can be devised on the nanometer length scale.
Introduction
In the classical planar MOSFET, the gate dielectric and gate electrode sit above the channel region. Electrostatic control of the channel by the gate is achieved through the capacitive coupling between the gate and the channel. To maintain transistor scaling laws, a reduction in the depths of the source and drain regions by the same factor as the gate length reduction is required. This reduces short-channel effects at the cost of rendering less effective the control of the channel region through source and drain voltages. High-κdielectrics are used as gate oxide materials to increase current drive without having to pay a stiff penalty in gate oxide leakage, which is in turn largely responsible for standby power consumption. Decreasing the equivalent gate oxide thickness (EOT) through the replacement of the silicon dioxide insulating layer by metallic oxides with higher dielectric constant improves the capacitive coupling between the gate and the channel, and thus also reduces short-channel effects.
The electrostatics of a planar, long-channel MOSFET can be reduced in a first approximation to a one-dimensional problem. Early textbooks on semiconductor device physics introduced the “gradual channel approximation,” which can be solved by Poisson's equation – the equation that governs the relationship between electric fields and electrical charges – in one dimension, vertically from the gate through the channel and down through the silicon substrate. Short-channel effects whereby electric fields from the source and the drain encroach laterally (horizontally) in the channel region introduce a second dimension to the problem. In planar MOSFETs on bulk silicon, short-channel effects become insurmountable once the gate length becomes smaller than approximately 15 to 20 nm.
Dedication
- Jean-Pierre Colinge, James C. Greer
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- Nanowire Transistors
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- 21 April 2016, pp v-vi
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Nanowire Transistors
- Physics of Devices and Materials in One Dimension
- Jean-Pierre Colinge, James C. Greer
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- 05 April 2016
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- 21 April 2016
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From quantum mechanical concepts to practical circuit applications, this book presents a self-contained and up-to-date account of the physics and technology of nanowire semiconductor devices. It includes a unified account of the critical ideas central to low-dimensional physics and transistor physics which equips readers with a common framework and language to accelerate scientific and technological developments across the two fields. Detailed descriptions of novel quantum mechanical effects such as quantum current oscillations, the metal-to-semiconductor transition and the transition from classical transistor to single-electron transistor operation are described in detail, in addition to real-world applications in the fields of nanoelectronics, biomedical sensing techniques, and advanced semiconductor research. Including numerous illustrations to help readers understand these phenomena, this is an essential resource for researchers and professional engineers working on semiconductor devices and materials in academia and industry.
Evolution of SOI MOSFETs: from Single Gate to Multiple Gates
- Jean-Pierre Colinge
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- Journal:
- MRS Online Proceedings Library Archive / Volume 765 / 2003
- Published online by Cambridge University Press:
- 01 February 2011, D1.6
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- 2003
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To improve short-channel characteristics and increase current drive, SOI technology is shifting focus from “classical” single-gate MOSFET architectures to multiple-gate device structures. This paper traces the history of single- and multiple-gate SOI MOSFETs and summarizes the electrical characteristics of such devices.
Silicon-on-lnsulator Technology
- Jean-Pierre Colinge, Robert W. Bower
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- Journal:
- MRS Bulletin / Volume 23 / Issue 12 / December 1998
- Published online by Cambridge University Press:
- 29 November 2013, pp. 13-15
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- December 1998
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Silicon-on-lnsulator (SOI) technology has been around since the 1960s when so-called silicon on sapphire (SOS) was first introduced. Silicon on sapphire has been used for many years for the fabrication of spaceborne and high-speed integrated circuits. It is still used in the fabrication of radio-frequency circuits.
More recent SOI materials involve only silicon and silicon dioxide—the two most common materials used in the fabrication of integrated circuits—as opposed to SOS, which requires the use of an alumina substrate.
Silicon-on-insulator technology has been used for a long time in niche applications such as spacecraft electronics and devices operating in a hightemperature or radiative environment. Recently however much attention has been paid to SOI technology because it is extremely suitable for the fabrication of low-voltage integrated circuits. Such circuits are in high demand for all kinds of portable systems, ranging from cellular phones to laptop computers. In August of 1998, IBM, Sharp, and other semiconductor manufacturers announced the development of SOI chips for high-speed computing and telecommunication con-sumer electronics. Most major semiconductor companies are putting considerable effort into SOI-circuit development for mainstream low-power applications.
Silicon-on-lnsulator Technology: Past Achievements and Future Prospects
- Jean-Pierre Colinge
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- Journal:
- MRS Bulletin / Volume 23 / Issue 12 / December 1998
- Published online by Cambridge University Press:
- 29 November 2013, pp. 16-19
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- December 1998
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In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.