Skip to main content
×
Home
Nanowire Transistors
  • Export citation
  • Recommend to librarian
  • Recommend this book

    Email your librarian or administrator to recommend adding this book to your organisation's collection.

    Nanowire Transistors
    • Online ISBN: 9781107280779
    • Book DOI: https://doi.org/10.1017/CBO9781107280779
    Please enter your name
    Please enter a valid email address
    Who would you like to send this to? *
    ×
  • Buy the print book

Book description

From quantum mechanical concepts to practical circuit applications, this book presents a self-contained and up-to-date account of the physics and technology of nanowire semiconductor devices. It includes a unified account of the critical ideas central to low-dimensional physics and transistor physics which equips readers with a common framework and language to accelerate scientific and technological developments across the two fields. Detailed descriptions of novel quantum mechanical effects such as quantum current oscillations, the metal-to-semiconductor transition and the transition from classical transistor to single-electron transistor operation are described in detail, in addition to real-world applications in the fields of nanoelectronics, biomedical sensing techniques, and advanced semiconductor research. Including numerous illustrations to help readers understand these phenomena, this is an essential resource for researchers and professional engineers working on semiconductor devices and materials in academia and industry.

Reviews

'This is a very interesting and advanced book that gives a deep introduction to and explanation of the physics behind nanowire transistors … It is well written, organized, and self-explanatory, and can be used as a reference by those who wish to enter into the field of nanowire and nanostructure-based electronics. The book has many up-to-date references and clear and precise text with plenty of figures and diagrams, and therefore is a fundamental resource. … This is a well-organized book wherein the preceding chapters are used as the basis for understanding the following ones. … [It] is suitable for graduate researchers in materials science and semiconductor devices as well as engineers who want deeper insight into the explanation of nanowire-based devices.'

Joana Vaz Pinto Source: MRS Bulletin

    • Aa
    • Aa
Refine List
Actions for selected content:
Select all | Deselect all
  • View selected items
  • Export citations
  • Download PDF (zip)
  • Send to Kindle
  • Send to Dropbox
  • Send to Google Drive
  • Send content to

    To send content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about sending content to .

    To send content to your Kindle, first ensure no-reply@cambridge.org is added to your Approved Personal Document E-mail List under your Personal Document Settings on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part of your Kindle email address below. Find out more about sending to your Kindle.

    Note you can select to send to either the @free.kindle.com or @kindle.com variations. ‘@free.kindle.com’ emails are free but can only be sent to your device when it is connected to wi-fi. ‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.

    Find out more about the Kindle Personal Document Service.

    Please be advised that item(s) you selected are not available.
    You are about to send:
    ×

Save Search

You can save your searches here and later view and run them again in "My saved searches".

Please provide a title, maximum of 40 characters.
×

This list contains references from the content that can be linked to their source. For a full set of references and notes please see the PDF or HTML where available.


[9] G.A. Armstrong , J.R. Davis , A. Doyle , “Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation,” IEEE Transactions on Electron Devices 38, pp. 328–336 (1991).

[10] K.E. Moselund et al., “Punch-through impact ionization MOSFET (PIMOS): from device principle to applications,” Solid-State Electronics 52, pp. 1336–1344 (2008).

[12] H. Lu , A. Seabaugh , “Tunnel field-effect transistors: state-of-the-art,” IEEE Journal of the Electron Device Society 2(4), pp. 44–49 (2014).

[13] A. Afzalian , J.P. Colinge , D. Flandre , “Physics of gate modulated resonant tunneling (RT)-FETs: multi-barrier MOSFET for steep slope and high on-current,” Solid-State Electronics 59, pp. 50–61 (2011).

[14] S. Salahuddin , S. Datta , “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Letters 8, pp. 405–410 (2008).

[15] V.V. Zhirnov , R.K. Cavin , “Nanoelectronics: negative capacitance to the rescue?,” Nature Nanotechnology 3(2), pp. 77–78 (2008).

[17] R.H. Dennard et al., “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Journal of Solid-State Circuits 9(5), pp. 256–268 (1974).

[22] A. Rahman et al., “Theory of ballistic nanotransistors,” IEEE Transactions on Electron Devices 50(9), pp. 1853–1864 (2003).

[23] K. Natori , “Ballistic metal-oxide-semiconductor field effect transistor,” Journal of Applied Physics 76(8), pp. 4879–4890 (1994).

[24] M.S. Lundstrom , Z. Ren , “Essential physics of carrier transport in nanoscale MOSFETs,” IEEE Transactions on Electron Devices 49(1), pp. 133–141 (2002).

[25] A. Khakifirooz , O.M. Nayfeh , D. Antoniadis , “A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices 56(8), pp. 1674–1680 (2009).

[26] A. Majumdar , D.A. Antoniadis , “Analysis of carrier transport in short-channel MOSFETs,” IEEE Transactions on Electron Devices 61(2), pp. 351–358 (2014).

[27] M.S. Lundstrom , D.A. Antoniadis , “Compact models and the physics of nanoscale FETs,” IEEE Transactions on Electron Devices 61(2), pp. 225–233 (2014).

[28] R. Wang et al., “Experimental investigations on carrier transport in Si nanowire transistors: ballistic efficiency and apparent mobility,” IEEE Transactions on Electron Devices 55(11), pp. 2960–2967 (2008).

[30] M. Salmani-Jelodar et al., “Transistor roadmap projection using predictive full-band atomistic modeling,” Applied Physics Letters 105, pp. 083508.1–4 (2014).

J.-P. Colinge (ed.), FinFETs and other Multigate Transistors, Springer (2008)

[4] T. Skotnicki et al., “Innovative materials, devices, and CMOS technologies for low-power mobile multimedia,” IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 96–130 (2008)

[5] T. Sekigawa , Y. Hayashi , “Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate,” Solid-State Electronics, vol. 27, no. 8–9, pp. 827–828 (1984)

[10] B.S. Doyle et al., “High performance fully-depleted tri-gate CMOS transistors,” IEEE Electron Device Letters, vol. 24, no. 4, pp. 263–265 (2003)

[14] J.P. Colinge et al., “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, pp. 225–229 (2010)

[15] L. Ansari et al., “Simulation of junctionless Si nanowire transistors with 3 nm gate length,” Applied Physics Letters, vol. 97, p. 062105 (2010)

[16] L. Ansari et al., “First principle-based analysis of single-walled carbon nanotube and silicon nanowire junctionless transistors,” IEEE Transactions on Nanotechnology, vol. 12, no. 6, pp. 1075–1081 (2013)

[17] F. Hofmann et al., “NVM based on FinFET device structures,” Solid-State Electronics, vol. 49, no. 11, pp. 1799–1804 (2005)

[18] X. Tang et al., “Self-aligned SOI nano flash memory device,” Solid State Electronics, vol. 44, pp. 2259–2264 (2000)

[22] J.P. Colinge , “Multiple-gate SOI MOSFETs,” Solid-State Electronics, vol. 48, no. 6, pp. 897–905 (2004)

[23] I. Ferain , C.A. Colinge , J.P. Colinge , “Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors,” Nature, vol. 479, pp. 310–316 (2011)

[24] K.J. Kuhn , “Considerations for Ultimate CMOS Scaling,” IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1813–1828 (2012)

[25] J. Goldberger et al., “Silicon vertically integrated nanowire field effect transistors,” Nano Letters, vol. 6, no. 5, pp. 973–977 (2006)

[26] R.H. Yan , A. Ourmazd , K.F. Lee , “Scaling the Si MOSFET: from bulk to SOI to bulk,” IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1704–1710 (1992)

[27] K. Suzuki et al., “Scaling theory for double-gate SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 40, no. 12, pp. 2326–2329 (1993)

[29] C.-W. Lee et al., “Device design guidelines for nano-scale MuGFETs,” Solid-State Electronics, vol. 51, pp. 505–510 (2007)

[30] C.P. Auth , J.D. Plummer , “Scaling theory for cylindrical, fully depleted, surrounding-gate MOSFET's,” IEEE Electron Device Letters, vol. 18, no. 2, pp. 74–76 (1997)

[31] T.-K. Chiang , “A novel scaling theory for fully depleted, multiple-gate MOSFET, including effective number of gates (ENGs),” IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 631–632 (2014)

[32] Bo Yu , L. Wang et al., “Scaling of nanowire transistors,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 2836–2858 (2008)

[34] C. Liu et al., “Negative-bias temperature instability in gate-all-around silicon nanowire MOSFETs: characteristic modeling and the impact on circuit aging,” IEEE Transactions on Electron Devices, vol. 57, no. 12, pp. 3442–3450 (2010)

[36] K. Nayak et al., “Metal-gate granularity-induced threshold voltage variability and mismatch in Si gate-all-around nanowire n-MOSFETs,” IEEE Transactions on Electron Devices, vol. 61, no. 12 (2014) DOI: 10.1109/TED.2014.2351401

[38] E. Moreno , J.B. Roldán , F.G. Ruiz , D. Barrera , A. Godoy , F. Gámiz , “An analytical model for square GAA MOSFETs including quantum effects,” Solid-State Electronics, vol. 54, pp. 1463–1469 (2010)

[40] F. Balestra et al., “Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance,” IEEE Electron Device Letters, vol. 8, pp. 410–412 (1987)

[41] J.P. Colinge , “Quantum-wire effects in trigate SOI MOSFETs,” Solid-State Electronics, vol. 51 –9, pp. 1153–1160 (2007)

[42] D. Jimenéz et al., “Unified compact model for the ballistic quantum wire and quantum well metal-oxide-semiconductor field-effect-transistor,” Journal of Applied Physics, vol. 94, pp. 1061–1068 (2003)

[43] S.C. Rustagi et al., “Low-temperature transport characteristics and quantum-confinement effects in gate-all-around Si-nanowire N-MOSFET,” IEEE Electron Device Letters, vol. 28, no. 10, pp. 909–912 (2007)

[44] J.P. Colinge et al., “A silicon-on-insulator quantum wire,” Solid-State Electronics, vol. 39, pp. 49–51 (1996)

[46] J.P. Colinge et al., “Low-temperature electron mobility in trigate SOI MOSFETs,” IEEE Electron Device Letters, vol. 27, no. 2, pp. 120–122, 2006

[48] H. Yoshioka et al., “Mobility oscillation by one-dimensional quantum confinement in Si-nanowire metal-oxide-semiconductor field effect transistors,” Journal of Applied Physics, vol. 106, p. 034312 (2009)

[49] K.S. Yi et al., “Room-temperature quantum confinement effects in transport properties of ultrathin Si nanowire field-effect transistors,” Nano Letters, vol. 11, no. 12, pp. 5465–5470 (2011)

[50] J.-T. Park , J.Y. Kim , C.-W. Lee , J.P. Colinge , “Low-temperature conductance oscillations in junctionless nanowire transistors,” Applied Physics Letters, vol. 97, p. 172101 (2010)

[52] X. Li et al., “Low-temperature electron mobility in heavily n-doped junctionless nanowire transistor,” Applied Physics Letters, vol. 102, p. 223507 (2013)

[55] M. Je , S. Han , I. Kim , H. Shin , “A silicon quantum wire transistor with one-dimensional subband effects,” Solid-State Electronics, vol. 44, pp. 2207–2212 (2000)

[57] M. Bescond et al., “Tight-binding calculations of Ge-nanowire bandstructures,” Journal of Computational Electronics, vol. 6, pp. 341–344 (2007)

[58] D. Jena , “Tunneling transistors based on graphene and 2-D crystals,” Proceedings of the IEEE, vol. 101, no. 7, pp. 1585–1602 (2013)

[60] M.A. Khayer , R.K. Lake , “Performance of n-type InSb and InAs nanowire field effect transistors,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 2939–2345 (2008)

[62] M.S. Dresselhaus , O. Rabin , “Carbon nanotubes and bismuth nanowires,” in Nanoengineering of Structural, Functional and Smart Materials, M.J. Schulz , A.D. Kelkar and M.J. Sundaresan (eds.), CRC Press (2005)

[63] S. Lee et al., “Direct observation of the semimetal-to-semiconductor transition of individual single-crystal bismuth nanowires grown by on-film formation of nanowires,” Nanotechnology, vol. 21, pp. 405701/1–6 (2010)

[65] A. Afzalian et al., “Quantum confinement effects in capacitance behavior of multigate silicon nanowire MOSFETs,” IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 300–309 (2011)

[66] E.G. Marin et al., “Analytical gate capacitance modeling of III–V nanowire transistors,” IEEE Transactions on Electron Devices, vol. 60, no. 5, pp. 1590–1599 (2013)

[68] N. Takiguchi et al., “Comparisons of performance potentials of Si and InAs nanowire MOSFETs under ballistic transport,” IEEE Transactions on Electron Devices, vol. 59, no. 1, pp. 206–211 (2012)

[69] E. Lind et al., “Band structure effects on the scaling properties of [111] InAs nanowire MOSFETs,” IEEE Transactions on Electron Devices, vol. 56, no. 2, pp. 201–205 (2009)

[70] J. Knoch , W. Riess , J. Appenzeller , “Outperforming the conventional scaling rules in the quantum capacitance limit,” IEEE Electron Device Letters, vol. 29, no. 4, pp. 372–374 (2008)

[72] M.V. Fischetti et al., “Theoretical study of some physical aspects of electronic transport in nMOSFETs at the 10-nm gate-length,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2116–2163 (2007)

[74] P. Razavi et al., “Influence of channel material properties on performance of nanowire transistors,” Journal of Applied Physics, vol. 111, no. 12, pp. 124509-1–124509-8 (2012)

[76] N. Neophytou et al., “On the bandstructure velocity and ballistic current of ultra-narrow silicon nanowire transistors as a function of cross section size, orientation, and bias,” Journal of Applied Physics, vol. 107, pp. 113701.1–9 (2010)

[77] N. Neophytou , H. Kosina , “Confinement-induced carrier mobility increase in nanowires by quantization of warped bands,” Solid-State Electronics, vol. 70, pp. 81–91 (2012)

[80] A. Boukai , Ke Xu , J.R. Heath , “Size-dependent transport and thermoelectric properties of individual polycrystalline bismuth nanowires,” Advanced Materials, vol. 18, pp. 864–869 (2006)

[81] Y.T. Tian et al., “Step-shaped bismuth nanowires with metal–semiconductor junction characteristics,” Nanotechnology, vol. 17, pp. 1041–1045 (2006)

[83] W. Shim et al., “On-film formation of Bi nanowires with extraordinary electron mobility,” Nano Letters, vol. 9, no. 1, pp. 18–22 (2009)

[84] L. Ansari et al., “A proposed confinement modulated gap nanowire transistor based on a metal (tin),” Nano Letters, vol. 12, no. 5, pp. 2222–2227 (2012)

[85] C.L. Kane , E.J. Mele , “Z2 topological order and the quantum spin Hall effect,” Physical Review Letters, vol. 95, no. 14, pp. 146802:1–4 (2005)

[88] N. Dehdashti Akhavan et al., “Nanowire to single-electron transistor transition in trigate SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 58, no. 1, pp. 26–32 (2011)

[89] V. Deshpande et al., “Scaling of trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to single electron transistor,” Solid-State Electronics, vol. 84, pp. 179–184 (2013)

[91] S. Barraud , M. Berthomé , R. Coquand , et al., “Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm,” IEEE Electron Device Letters, vol. 33, no. 9, pp. 1225–1227 (2012)

[94] A. Ionescu , H. Riel , “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329–337 (2011)

[98] A. Vandooren et al., “Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs,” Solid-State Electronics, vol. 72, pp. 82–87 (2012)

[100] R. Gandhi et al., “CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤ 50-mV/decade subthreshold swing,” IEEE Electron Device Letters, vol. 32, no. 11, pp. 1504–1506 (2011)

[103] J. Wan et al., “Novel bipolar-enhanced tunneling FET with simulated high on-current,” IEEE Electron Device Letters, vol. 34, no. 1, pp. 24−26 (2013)

[3] S. Barraud , et al., “Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm,” IEEE Electron Device Letters, vol. 33, no. 11, pp. 1526–1528 (2012)

[6] R.G. Hobbs et al., “Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography,” Journal of Vacuum Science and Technology B, vol. 30, no. 4, pp. 041602.1–7 (2012)

[8] R.A. Farrell et al., “Large-scale parallel arrays of silicon nanowires via block copolymer directed self-assembly,” Nanoscale, vol. 4, pp. 3228–3236 (2012)

[9] S. Rasappa et al., “Fabrication of a sub-10 nm silicon nanowire based ethanol sensor using block copolymer lithography,” Nanotechnology, vol. 24, no. 6, p. 065503 (2013)

[10] Y.-K. Choi et al., “Fabrication of Sub-10-nm silicon nanowire arrays by size reduction lithography,” Journal of Physical Chemistry B, vol. 107, pp. 3340–3343 (2003)

[13] G.F. Cerofolini , P. Amato , E. Romano , “The multi-spacer technique: a non-lithographic technique for terascale integration,” Semiconductor Science and Technology, vol. 23, p. 075020 (2008)

[15] D.-I. Moon et al., “Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate,” IEEE Transactions on Electron Devices, vol. 60, no.4, pp. 1355–1360 (2013)

[18] M. Jurczak et al., “Silicon-on-nothing (SON) – an innovative process for advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, no. 11, pp. 2179–2187 (2000)

[28] N. Singh et al., “Si, SiGe nanowire devices by top–down technology and their applications,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3107–3118 (2008)

[30] R.G. Treuting , S.M. Arnold , “Orientation habits of metal whiskers,” Acta Metallurgica, vol. 5, no. 10, p. 598 (1957)

[31] M. Hasan , M.F. Huq , Z.H Mahmood , “A review on electronic and optical properties of silicon nanowire and its different growth techniques,” SpringerPlus, vol. 2, p. 151 (2013)

[32] R.S. Wagner , W.C. Ellis , “Vapor-liquid-solid mechanism of single crystal growth,” Applied Physics Letters, vol. 4, no. 5, pp. 89–90 (1964)

[33] V. Schmidt , J.V. Wittemann , U. Gösele , “Growth, thermodynamics, and electrical properties of silicon nanowires,” Chemical Reviews, vol. 110, no. 1, pp. 361–388 (2010)

[34] E.I. Givargizov , “Fundamental aspects of VLS growth,” Journal of Crystal Growth, vol. 31, pp. 20–30 (1975)

[35] E.I. Givargizov , Y.G. Kostyuk , “Controlled growth of oriented systems of whisker crystals,” РОСТ КРИСТАЛЛОВ (Growth of Crystals), Springer, pp. 276–283 (1975)

[36] G.A. Bootsma , H.J. Gassen , “A quantitative study on the growth of silicon whiskers from silane and germanium whiskers from germane,” Journal of Crystal Growth, vol. 10, no. 3, pp. 223–234 (1971)

[39] N.J. Quitoriano , T.I. Kamins , “Integratable nanowire transistors,” Nano Letters, vol. 8, no 12, pp. 4410–4414 (2008)

[40] S.J. Whang et al., “Complementary metal-oxide-semiconductor compatible Al-catalyzed silicon nanowires: growth and the effects of surface oxidation of Al seeding layer,” Electrochemical and Solid-State Letters, vol. 10, no. 6, pp. E11–E13 (2007)

[41] T.I. Kamins et al., “Ti-catalyzed Si nanowires by chemical vapor deposition: Microscopy and growth mechanisms,” Journal of Applied Physics, vol. 89, no. 2, pp. 1008–1016 (2001)

[42] S.J. Rathi et al., “Tin-catalyzed plasma-assisted growth of silicon nanowires,” Journal of Physical Chemistry C, vol. 115, pp. 3833–3839 (2011)

[43] B. Mandl et al., “Growth mechanism of self-catalyzed group III-V nanowires,” Nano Letters, vol. 10, pp. 4443–4449 (2010)

[44] S. Sasaki et al., “Encapsulated gate-all-around InAs nanowire field-effect transistors,” Applied Physics Letters, vol. 103, pp. 213502(1–5) (2013)

[45] T. Mårtensson et al., “Epitaxial growth of indium arsenide nanowires on silicon using nucleation templates formed by self-assembled organic coatings,” Advanced Materials, vol. 19, no. 14, pp. 1801–1806 (2007)

[46] C. Rehnstedt et al., “Vertical InAs nanowire wrap gate transistors on Si substrates,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3037–3041 (2008)

[47] K. Tomioka , J. Motohisa , S. Hara , T. Fukui , “Control of InAs nanowire growth directions on Si,” Nano Letters, vol. 8, no. 10, pp. 3475–3480 (2008)

[48] T. Tanaka et al., “Vertical surrounding gate transistors using single InAs nanowires grown on Si substrates,” Applied Physics Express, vol. 3, pp. 025003.1–3 (2010)

[49] M.R. Goulding , “The selective epitaxial growth of silicon,” Material Science and Engineering B, Solid State Materials for Advanced Technology, vol. 17, no. 1–3, pp. 47–67 (1993)

[50] W.-S. Cheong , “Optimization of selective epitaxial growth of silicon in LPCVD,” ETRI Journal, vol. 25, no. 6, pp. 503–509 (2003)

[52] L.-E. Wernersson et al., “III-V nanowires – extending a narrowing road,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2047–2060 (2010)

[53] L. Chen , W.Y. Fung , W. Lu , “Vertical nanowire heterojunction devices based on a clean Si/Ge interface,” Nano Letters, vol. 13, no. 11, pp. 5521–5527 (2013)

[55] M.T. Björk et al., “One-dimensional heterostructures in semiconductor nanowhiskers,” Applied Physics Letters, vol. 80, no. 6, pp. 1058–1060 (2002)

[56] K.E. Moselund et al., “InAs–Si nanowire heterojunction tunnel FETs,” IEEE Electron Device Letters, vol. 33, no. 10, pp. 1453–1455 (2012)

[57] A. Shik et al., “Electrical properties and band diagram of InSb-InAs nanowire type-III heterojunctions,” Journal of Applied Physics, vol. 113, pp. 104307.1–8 (2013)

[58] A.W. Dey , et al., “Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors,” Nano Letters, vol. 13, no. 12, pp. 5919−5924 (2013)

[59] K. Tomioka , T. Fukui , “Recent progress in integration of III–V nanowire transistors on Si substrate by selective-area growth,” Journal of Physics D: Applied Physics, vol. 47, no. 39, pp. 394001.1–12 (2014)

[60] L.J. Lauhon et al., “Epitaxial core-shell and core multishell nanowire heterostructures,” Nature, vol. 420, pp. 57–61 (2002)

[61] A.B. Greytak et al., “Growth and transport properties of complementary germanium nanowire field-effect transistors,” Applied Physics Letters, vol. 84, no. 21, pp. 4176–4178 (2004)

[62] W. Lu et al., “One-dimensional hole gas in germanium silicon nanowire heterostructures,” Proceedings of the National Academy of Sciences of the United States of America (PNAS), vol. 102, no. 29, pp. 10046–10051 (2005)

[63] J. Xiang , W. Lu , Y. Yu , Y. Wu , H. Yan , C.M. Lieber , “Ge/Si nanowire heterostructures as high-performance field-effect transistors,” Nature, vol. 441, no. 25, pp. 489–493 (2006)

[64] S.A. Dayeh , A.V. Gin , S.T. Picraux , “Advanced core/multishell germanium/silicon nanowire heterostructures: morphology and transport,” Applied Physics Letters, vol. 98, no. 16, pp. 163112.1–3 (2011)

[65] X. Peng , P. Logan , “Electronic properties of strained Si/Ge core-shell nanowires,” Applied Physics Letters, vol. 96, no. 14, pp. 143119.1–3 (2010)

[68] T.E. Trammell et al., “Equilibrium strain-energy analysis of coherently strained core-shell nanowires,” Journal of Crystal Growth, vol. 310, no. 12, pp. 3084–3092 (2008)

[71] W. Xiong et al., “Improvement of FinFET electrical characteristics by hydrogen annealing,” IEEE Electron Device Letters, vol. 25, no. 8, pp. 541–543 (2004)

[74] H.I. Liu et al., “Self-limiting oxidation for fabricating sub-5 nm silicon nanowires,” Applied Physics Letters, vol. 64, no. 11, pp. 1383–1385 (1994)

[75] P.-F. Fazzini et al., “Modeling stress retarded self-limiting oxidation of suspended silicon nanowires for the development of silicon nanowire-based nanodevices,” Journal of Applied Physics, vol. 110, pp. 033524.1–8 (2011)

[76] D.-B. Kao et al., “Two-dimensional thermal oxidation of silicon – II. Modeling stress effects in wet oxides,” IEEE Transactions on Electron Devices, vol. 35, no. 1, pp. 25–37 (1988)

[77] C.C. Büttner , M. Zacharias , “Retarded oxidation of Si nanowires,” Applied Physics Letters, vol. 89, pp. 263106(1–3) (2006)

[79] U. Khalilov et al., “Self-limiting oxidation in small-diameter Si nanowires,” Chemistry of Materials, vol. 24, pp. 2141−2147 (2012)

[80] E.J. Boyd , D. Uttamchandani , “Measurement of the anisotropy of Young's modulus in single-crystal silicon,” Journal of Microelectromechanical Systems, vol. 21, no. 1, pp. 243–249 (2012)

[81] J.J. Wortman , R.A. Evans , “Young's modulus, shear modulus, and Poisson's ratio in silicon and germanium,” Journal of Applied Physics, vol. 36, no. 1, pp. 153–156 (1965)

[82] Y. Zhu et al., “Mechanical properties of vapor-liquid-solid synthesized silicon nanowires,” Nano Letters, vol. 9, no. 11, pp. 3934–3939 (2009)

[83] X. Han et al., “Low-temperature in situ large-strain plasticity of silicon nanowires,” Advanced Materials, vol. 19, no. 16, pp. 2112–2118 (2007)

[84] S.M. Cea et al., “Process modeling for advanced device technologies,” Journal of Computational Electronics, vol. 13, pp. 18–32 (2014)

[85] P. Alekseev et al., “Measurement of Young's modulus of GaAs nanowires growing obliquely on a substrate,” Semiconductors, vol. 46, no. 5, pp. 641–646 (2012)

[86] B. Lee , R.E. Rudd , “First-principles study of the Young's modulus of Si <001> nanowires,” Physical Review B, vol. 75, pp. 041305(1–4) (2007)

[87] P.W. Leu , A. Svizhenko , K. Cho , “Ab initio calculations of the mechanical and electronic properties of strained Si nanowires,” Physical Review B, vol. 77, pp. 235305(1–14) (2008)

[88] K.E. Petersen , “Silicon as a mechanical material,” Proceedings of the IEEE, vol. 70, no. 5, pp. 420–456 (1982)

[90] K. Kang , W. Cai , “Size and temperature effects on the fracture mechanisms of silicon nanowires: molecular dynamics simulations,” International Journal of Plasticity, vol. 26, pp. 1387–1401 (2010)

[91] H. Sadeghian et al., “On the size-dependent elasticity of silicon nanocantilevers: impact of defects,” Journal of Physics D: Applied Physics, vol. 44, pp. 072001.1–6 (2011)

[92] H. Schlötterer , “Mechanical and electrical properties of epitaxial silicon films on spinel,” Solid-State Electronics, vol. 11, no. 10, pp. 947–956 (1968)

[93] T. Sato et al., “CMOS/SOS VLSI Technology,” in Comparison of Thin-film Transistor and SOI Technologies, H.W. Lam , M.J. Thompson (eds.), Materials Research Society Symposium Proceedings, vol. 33, pp. 25–34 (1984)

[94] M. Chu et al., “Strain: a solution for higher carrier mobility in nanoscale MOSFETs,” Annual Review of Materials Research, vol. 39, pp. 203–229 (2009)

[97] S.E. Thompson et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices, vol. 51, no. 11, pp. 1790–1797 (2004)

[99] F. Andrieu et al., “Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node,” Microelectronic Engineering, vol. 84, no. 9–10, pp. 2047–2053 (2007)

[100] M.V. Fischetti , S.E. Laux , “Band structure, deformation potentials, and carrier mobility in strained-Si, Ge, and SiGe alloys,” Journal of Applied Physics, vol. 80, pp. 2234–2252 (1996)

[101] M.V. Fischetti , F. Gámiz , W. Hänsch , “On the enhanced electron mobility in strained-silicon inversion layers,” Journal of Applied Physics, vol. 92, pp. 7320–7324 (2002)

[102] Y.M. Niquet , C. Delerue , C. Krzeminski , “Effects of strain on the carrier mobility in silicon nanowires,” Nano Letters, vol. 12, pp. 3545–3550 (2012)

[103] Y.M. Niquet , C. Delerue , “Carrier mobility in strained Ge nanowires,” Journal of Applied Physics, vol. 112, pp. 084301.1–4 (2012)

[105] J.P. Raskin et al., “Mobility improvement in nanowire junctionless transistors by uniaxial strain,” Applied Physics Letters, vol. 97, pp. 042114.1–3 (2010)

[106] M.P. Persson et al., “Charged impurity scattering and mobility in gated silicon nanowires,” Physical Review B, vol. 82, pp. 115318.1–8 (2010)

[107] Y.M. Niquet , H. Mera , C. Delerue , “Impurity-limited mobility and variability in gate-all-around silicon nanowires,” Applied Physics Letters, vol. 100, pp. 153119.1–4 (2012)

[1] W.R. Frensley , “Boundary conditions for open quantum systems driven far from equilibrium,” Rev. Mod. Phys., vol. 62, pp. 745–791, 1990.

[3] C.C.J. Roothaan , “New developments in molecular orbital theory,” Rev. Mod. Phys., vol. 23, pp. 69–89, 1951.

[5] J.C. Slater and G.F. Koster , “Simplified LCAO method for the periodic potential problem,” Phys. Rev., vol. 94, pp. 1498–1524, 1954.

[6] M.C. Payne , M.P. Teter , D.C. Allan , T.A. Arias , and J.D. Joannopoulos , “Iterative minimization techniques for ab initio total energy calculations: molecular dynamics and conjugate gradients,” Rev. Mod. Phys., vol. 64, pp. 1045–1097, 1992.

[7] J.M. Foster and S.F. Boys , “Canonical configuration interaction method,” Rev. Mod. Phys., vol. 32, pp. 300–302, 1960.

[8] G.H. Wannier , “The structure of electronic excitations in insulating crystals,” Phys. Rev., vol. 52, pp. 191–197, 1937.

[9] N. Marzari , A.A. Mostofi , J.R. Yates , I. Souza , and D. Vanderbilt , “Maximally localized Wannier functions: theory and application,” Rev. Mod. Phys., vol. 84, pp. 1419–1475, 2012.

[10] B.A. Joyce , “Molecular beam epitaxy,” Rep. Prog. Phys., vol. 48, pp. 1637–1697, 1985.

R. M. Martin , Electronic Structure: Basic Theory and Practical Methods, Cambridge: Cambridge University Press, 2004.

I. Shavitt and R. J. Bartlett , Many-Body Methods in Chemistry and Physics, Cambridge: Cambridge University Press, 2009.

[2] W. Paul , “Band structure of the intermetallic semiconductors from pressure experiments,” J. Appl. Phys., vol. 32, pp. 2082–2094, 1961.

[3] S. Fahy and J. C. Greer , “Alloy corrections to the virtual crystal approximation and explicit band structure calculations for silicon-germanium,” Mat. Sci. in Semicond. Proc., vol. 3, pp. 109–114, 2000.

[5] C. M. Wolfe , G. E. Stillman , and W. T. Lindley , “Electron mobility in high purity GaAs,” J. Appl. Phys., vol. 41, pp. 3088–3091, 1970.

[6] I. Vurgaftman , J. R. Meyer , and L. R Ram-Mohan , “Band parameters for III-V compound semiconductors and their alloys,” J. Appl. Phys., vol. 89, pp. 5815–5875, 2001.

[9] J. J. J. Gu et al., “Size-dependent-transport study of In0.53Ga0.47As gate-all-around nanowire MOSFETs: impact of quantum confinement and volume inversion,” IEEE Electr. Dev. Lett., vol. 33, pp. 967–969, 2012.

[10] Y. Takeda , A. Sasaki , Y. Imamura , and T. Takagi , “Electron mobility and energy gap of In0.53Ga0.47As on InP substrate,” J. Appl. Phys., vol. 47, pp. 5405–5408, 1976.

[11] K. S. Novoselov , A. K. Geim , S. V. Morozov , et al., “Electric field effect in atomically thin carbon films,” Science, vol. 306, pp. 666–669, 2004.

[13] B. Long , M. Manning , M. Burke , et al., “Non-covalent functionalization of graphene using self-assembly of alkane-amines,” Adv. Funct. Mater., vol. 22, pp. 717–725, 2012.

[15] S. Iijima , “Helical microtubules of graphitic carbon,” Nature, vol. 354, pp. 56–58, 1991.

[17] J. Svensson and E. E. B. Campbell , “Schottky barriers in carbon nanotube-metal contacts,” J. Appl. Phys., vol. 110, pp. 111101-1–111101-16, 2011.

[18] S. L. T. Jones , G. Greene-Diniz , M. G. Haverty , S. Shankar , and J. C. Greer , “Effects of structure on the electronic properties of the iron-carbon nanotube interface,” Chem. Phys. Lett., vol. 615, pp. 11–15, 2014.

[19] J. Guo , S. Hasan , A. Javey , G. Bosman , and M. Lundstrom , “Assessment of high frequency performance of carbon nanotube transistors,” IEEE Trans. Nanotech., vol. 4, pp. 715–721, 2005.

[21] Q. H. Wang , K. K. Kalantar-Zadeh , A. Kis , J. N. Coleman , and M. S. Strano , “Electronics and optoelectronics of two-dimensional transition metal dichalcogenides,” Nature Nanotech., vol. 7, pp. 699–712, 2012.

[22] Y. Canivez , “Quick and easy measurement of the band gap in semiconductors,” Eur. J. Phys., vol. 4, pp. 42–44, 1983.

[24] J. Tauc , Optical Properties of Amorphous Semiconductors, New York: Plenum Publishers, 1974.

[25] J. A. Kubby and J. J. Boland , “Scanning tunneling microscopy of semiconductor surfaces,” Surf. Sci. Rep., vol. 26, pp. 61–204, 1996.

[26] N. Nilius , T. M. Wallis , and W. Ho , “Development of a one-dimensional band structure in artificial gold chains,” Science, vol. 297, pp. 1853–1856, 2002.

[27] X. Lu , M. Grobis , K. H. Khoo , S. G. Louie , and M. F. Crommie , Phys. Rev. Lett., vol. 90, pp. 096802-1–096802-4, 2003.

[28] J. A. Larsson , S. D. Elliott , J. C. Greer , J. Repp , G. Meyer , and R. Allensprach , “Orientation of single C60 molecules adsorbed on Cu(111): low temperature scanning tunnelling microscopy and density functional calculations,” Phys. Rev. B, vol. 77, pp. 115434-1–115434-9, 2008.

[29] J. Bardeen , “Tunnelling from a many-particle point of view,” Phys. Rev. Lett., vol. 6, pp. 57–59, 1961.

[30] R. M. Feenstra , J. A. Stroscio , and A. P. Fein , “Tunneling spectroscopy of the Si(111) 2x1 surface,” Surface Science, vol. 181, pp. 295–306, 1987.

[31] D. D. D. Ma , C. S. Lee , F. C. K. Au , S. Y. Tong , and S. T. Lee , “Small-diameter silicon nanowire surfaces,” Science, vol. 299, pp. 1874–1877, 2003.

[32] A. Damascelli , Z. Hussain , and Z.-X. Shen , “Angle-resolved photoemission studies of the cuprate superconductors,” Rev. Mod. Phys., vol. 75, pp. 473–539, 2003.

[34] W. Heisenberg , “Über quantentheoretische Umdeutung kinematischer und mechanischer Beziehungen,” Z. für Physik., vol. 33, pp. 879–893, 1925.

[36] P. A. M. Dirac , “On the theory of quantum mechanics,” Proc. Roy. Soc. A, vol. 112, pp. 661–677, 1926.

[37] D. R. Hartree , “The wave mechanics of an atom with a non-Coulomb central field: part I, theory and methods,” Proc. Camb. Phil. Soc., vol. 24, pp. 89–110, 1928.

[38] V. Fock , “Näherungsmethode zur Lösung des quantenmechanischen Mehrkörperproblems,” Z. Physik, vol. 61, pp. 126–148, 1930.

[39] P. A. M. Dirac , “Quantum mechanics of many-electron systems,” Proc. Roy. Soc. London A, vol. 123, pp. 714–733, 1929.

[40] J. C. Slater , “The theory of complex spectra,” Phys. Rev., vol. 34, 1293–1322, 1929.

[41] T. Koopmans , “Über die Zuordnung von Wellenfunktionen und Eigenwerten zu den einzelnen Elektronen eines Atoms,” Physica, vol. 1, pp. 104–113, 1934.

[42] B. T. Pickup and O. Goscinski , “Direct calculation of ionization energies,” Mol. Phys., vol. 26, pp. 1013–1035, 1973.

[44] E. Wigner , “On the interaction of electrons in metals,” Phys. Rev., vol. 46, pp. 1002–1011, 1934.

[45] L. H. Thomas , “The calculation of atomic fields,” Proc. Cambridge Phil. Soc., vol. 23, pp. 542–548, 1927.

[47] P. Hohenberg and W. Kohn , “Inhomogeneous electron gas,” Phys. Rev., vol. 136, pp. B864–B871, 1964.

[48] W. Kohn and L. J. Sham , “Self-consistent equations including exchange and correlation effects,” Phys. Rev., vol. 140, pp. A1133–A1138, 1965.

[49] I. Yeriskin , S. McDermott , R. J. Bartlett , G. Fagas and J. C. Greer , “Electronegativity and electron currents in molecular tunnel junctions,” J. Phys. Chem. C, vol. 114, pp. 20564–20568, 2010.

[50] A. Beste and R. J. Bartlett , “Independent particle theory with electron correlation,” J. Chem. Phys., vol. 120, pp. 8395–8404, 2004.

[54] J. B. Neaton , M. S. Hybertsen and S. G. Louie , “Renormalization of molecular electronic levels at metal-molecule interfaces,” Phys. Rev. Lett., vol. 97, pp. 216405-1–216405-4, 2006.

[55] J. M. Garcia-Lastra , C. Rostgaard , A. Rubio , and K. S. Thygesen , “Polarization-induced renormalization of molecular levels at metallic and semiconducting surfaces,” Phys. Rev. B, vol. 80, pp. 245427-1–245427-7, 2009.

[57] F. Stern and W. E. Howard , “Properties of semiconductor inversion layers in the electric quantum limit,” Phys. Rev. B, vol. 163, pp. 816–835, 1967.

[58] L. Huang , N. Lu , J.-A. Yan , M. Y. Chou , C.-Z. Wang , and K.-M. Ho , “Size and strain-dependent electronic structures in H-passivated Si [112] nanowires,” J. Chem. Phys. C, vol. 112, pp. 15680–15683, 2008.

[59] J.-A. Yan and M.-Y. Chou , “Size and orientation dependence in the electronic properties of silicon nanowires,” Phys. Rev. B, vol. 76, pp. 115319-1–115319-6, 2007.

[60] X. Zhao , C. M. Wei , L. Yang , and M. Y. Chou , “Quantum confinement and electronic properties in silicon nanowires,” Phys. Rev. Lett., vol. 92, pp. 236805-1–236805-4, 2004.

[62] M. Nolan , S. 'Callaghan , G. Fagas and J. C. Greer , “Silicon nanowire band gap modification,” Nano Lett., vol. 7, pp. 34–38, 2007.

[64] Y. M. Niquet , A. Lherbier , N. H. Quang , M. V. Fernández-Serra , X. Blasé , and C. Delerue , “Electronic structure of semiconductor nanowires,” Phys. Rev. B, vol. 73, pp. 165319-1–165319-13, 2006.

S. Datta , Electronic Transport in Mesoscopic Systems, Cambridge: Cambridge University Press, 1995.

D.K. Ferry and S.M. Goodnick , Transport in Nanostructures, Cambridge: Cambridge University Press, 1997.

G.D. Mahan , Many-Particle Physics, New York: Kluwer Academic/Plenum Publishers, 2000.

E.N. Economou , Green's Functions in Quantum Physics, Berlin: Springer Verlag, 2006.

[1] N. Mingo , L. Yang , D. Li , and A. Majumdar , “Predicting the thermal conductivity of silicon and germanium nanowires,” Nano Lett., vol. 3, pp. 1713–1716, 2003.

[2] E. Pop , S. Sinha , and K.E. Goodson , “Heat generation and transport in nanometer-scale transistors,” Proc. IEEE, vol. 94, pp. 1587–1601, 2006.

[4] R. Landauer , “Spatial variation of currents and fields due to localized scatterers in metallic conduction,” IBM J. Res. Devel., vol. 1, pp. 223–231, 1957.

[5] J.C. Greer , “Variational method with scattering boundary conditions imposed by the Wigner function,” Phys. Rev. B, vol. 83, pp. 245413-1–245413-11, 2011.

[6] L. Weber and E. Gmelin , “Transport properties of silicon,” Appl. Phys. A, vol. 53, pp. 136–140, 1991.

[7] D.M. Caughey and R.E. Thomas , “Carrier mobilities in silicon empirically related to doping and field,” Proc. IEEE, vol. 55, pp. 2192–2193, 1967.

[9] R. Rurali , T. Markussen , J. Suñé , M. Brandbyge , and A.-P. Jauho , “Modeling transport in ultra-thin silicon nanowires: charged versus neutral impurities,” Nano Lett., vol. 8, pp. 2825–2828, 2008.

[10] M. Diarra , Y.-M. Niquet , C. Delerue , and G. Allan , “Ionization energy of donor and acceptor impurities in semiconductor nanowires: Importance of dielectric confinement,” Phys. Rev. B, vol. 75, pp. 045301-1–045301-4, 2007.

[11] L. Ansari , B. Feldman , G. Fagas , J.-P. Colinge , and J.C. Greer , “Sub-threshold behavior of junctionless silicon nanowire transistors from atomic scale simulations,” Solid-State Elect., vol. 71, pp. 58–62, 2012.

[12] M.V. Fischetti , D.A. Neumayer , and E.A. Cartier , “Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: the role of remote phonon scattering,” J. Appl. Phys., vol. 90, pp. 4587–4608, 2001.

[13] R. Chau , S. Datta , M. Doczy , B. Doyle , J. Kavalieros , and M. Metz , “High-/metal-gate stack and its MOSFET characteristics,” IEEE Elect. Dev. Lett., vol. 25, pp. 408–410, 2004.

[14] M. Heyns and W. Tsai (eds.), “Ultimate scaling of CMOS logic devices with Ge and III–V materials,” MRS Bulletin, vol. 34, 2009.

[15] S. Monaghan , J.C. Greer , and S.D. Elliott , “Atomic scale model interfaces between high-k hafnium silicates and silicon,” Phys. Rev. B, vol. 75, pp. 245304-1–245304-14, 2007.

[16] H. Sakaki , “Scattering suppression and high-mobility effect of size-quantized electrons in ultrafine semiconductor wire structures,” Jpn. J. Appl. Phys., vol. 19, pp. L735–L738, 1980.

[17] F. Murphy-Armando and S. Fahy , “First-principles calculation of carrier-phonon scattering in n-type Si1−xGex alloys,” Phys. Rev. B, vol. 78, pp. 035202-1–035201-14, 2008.

[18] J.C. Mikkelsen Jr. and J.B. Boyce , “Atomic-scale structure of random solid solutions: extended X-ray-absorption fine-structure study of Ga1−xInxAs,” Phys. Rev. Lett., vol. 49, pp. 1412–1415, 1982.

[19] J.B. Hannon , S. Kodambaka , F.M. Ross , and R.M. Tromp , “The influence of the surface migration of gold on the growth of silicon nanowires,” Nature, vol. 440, pp. 69–71, 2006.

[20] Z. Wu , J.B. Neaton , and J.C. Grossman , “Quantum confinement and electronic properties of tapered silicon nanowires,” Phys. Rev. Lett., vol. 100, pp. 246804-1–246804-4, 2008.

[21] A. Lherbier , M. Persson , Y.-M. Niquet , F. Triozon , and S. Roche , “Quantum transport length scales in silicon-based semiconducting nanowires: surface roughness effects,” Phys. Rev. B, vol. 77, pp. 085301-1–085301-5, 2008.

[22] E.B. Ramayya , D. Vasileska , S.M. Goodnick , and I. Knezevic , “Electron transport in silicon nanowires: The role of acoustic phonon confinement and surface roughness scattering,” J. Appl. Phys., vol. 104, pp. 063711-1–063711-14, 2008.

[23] K.W. Adu , H.R. Gutiérrez , U.J. Kim , G.U. Sumanasekera , and P.C. Eklund , “Confined phonons in Si nanowires,” Nano Lett., vol. 5, pp. 409–414, 2005.

[24] M. Luisier and G. Klimeck , “Atomistic full-band simulations of silicon nanowire transistors: effects of electron-phonon scattering,” Phys. Rev. B, vol. 80, pp. 155430-1–1554301-11, 2009.

[25] F. Murphy-Armando , G. Fagas , and J.C. Greer , “Deformation potentials and electron-phonon coupling in silicon nanowires,” Nano Lett., vol. 10, pp. 869–873, 2010.

[26] F.D.M. Haldane , “Luttinger liquid theory of one-dimensional quantum fluids. I. Properties of the Luttinger model and their extension to the general 1D interacting spinless Fermi gas,” J. Phys. C: Solid State Phys., vol. 14, pp. 2585–2609, 1981.

[27] C.L. Kane and M.P.A. Fisher , “Transmission through barriers and resonant tunneling in an interacting one-dimensional electron gas,” Phys. Rev. B, vol. 46, pp. 15233–15262, 1992.

[28] P. Delaney and J.C. Greer , “Correlated electron transport in molecular electronics,” Phys. Rev. Lett., vol. 93, pp. 036805–036808, 2004.

[29] G. Fagas and J.C. Greer , “Tunnelling in alkanes anchored to gold electrodes via amine groups,” Nanotechnology, vol. 18, pp. 424010-1–424010-4, 2007.

[31] P.W. Anderson , D.J. Thouless , E. Abrahams , and D.S. Fisher , “New method for a scaling theory of localization,” Phys. Rev. B, vol. 22, pp. 3519–3526, 1980.

[32] T. Markussen , R. Rurali , A.-P. Jauho , and M. Brandbyge , “Scaling theory put into practice: first-principles modeling of transport in doped silicon nanowires,” Phys. Rev. Lett., vol. 99, pp. 076803-1–076803-4, 2007.

[34] G. Fagas and J.C. Greer , “Ballistic conductance in oxidized Si nanowires,” Nano Lett., vol. 9, pp. 1856–1860, 2009.

[39] R. Lake and S. Datta , “Non-equilibrium Green's function method applied to double-barrier resonant-tunneling diodes,” Phys. Rev. B, vol. 45, pp. 6670–6685, 1992.

[40] M. Brandbyge , J.-L. Mozos , P. Ordejón , J. Taylor , and K. Stokbro , “Density-functional method for nonequilibrium electron transport,” Phys. Rev. B, vol. 65, pp. 165401-1–165401-17, 2002.

[41] C. Grosche , “Path integration via summation of perturbation expansions and applications to totally reflecting boundaries, and potential steps,” Phys. Rev. Lett., vol. 71, pp. 1–4, 1993.

[42] M.A.M. de Aguiar , “Exact Green's function for the step and square-barrier potentials,” Phys. Rev. A., vol. 48, pp. 2567–2573, 1993.

[44] S.-H. Ke , H.U. Baranger , and W. Yang , “Electron transport through molecules: Self-consistent and non-self-consistent approaches,” Phys. Rev. B, vol. 70, pp. 085410-1–085410-12, 2004.

[45] D. Sharma , L. Ansari , B. Feldman , M. Iakovidis , J.C. Greer , and G. Fagas , “Transport properties and electrical device characteristics with the TiMeS computational platform: application in silicon nanowires,” J. Appl. Phys., vol. 113, pp. 203708-1–203708-8, 2013.

[1] A. Fadavi Roudsari et al., “Junction-less phototransistor with nanowire channels, a modeling study,” Optics Express, vol. 22, no. 10, pp. 12573–12582 (2014)

[2] T. Ernst et al., “Ultra-dense silicon nanowires: a technology, transport and interfaces challenges insight,” Microelectronics Engineering, vol. 88, pp. 1198–1202 (2011)

[5] K.J. Kuhn et al., “Process technology variation,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2197–2208 (2011)

[6] A. Bindal et al., “The design of dual work function CMOS transistors and circuits using silicon nanowire technology,” IEEE Transactions on Nanotechnology, vol. 6, no. 3, pp. 291–302 (2007)

[7] A. Bindal , S. Hamedi-Hagh , “Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic,” IET Science, Measurement and Technology, vol. 1, no. 2, pp. 121–130 (2007)

[8] S. Sato et al., “Electrical characteristics of asymmetrical silicon nanowire field-effect transistors,” Applied Physics Letters, vol. 99, pp. 223518/1–3 (2011)

[9] K. Sakui , T. Endoh , “A new vertical MOSFET ‘vertical logic circuit (VLC) MOSFET’ suppressing asymmetric characteristics and realizing an ultra compact and robust logic circuit,” Solid-State Electronics, vol. 54, pp. 1457–1462 (2010)

[13] S. Maheshwaram et al., “Vertical nanowire CMOS parasitic modeling and its performance analysis,” IEEE Transactions on Electron Devices, vol. 60, no. 9, pp. 2943–2949 (2013)

[16] K. Nayak et al., “CMOS logic device and circuit performance of Si gate all around nanowire MOSFET,” IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3066–3074 (2014)

[19] A. Kranti et al., “Junctionless 6T SRAM cell,” Electronics Letters, vol. 46, no. 22, pp. 1491–1493 (2010)

[20] Y.-B. Liao et al., “Assessment of structure variation in silicon nanowire FETs and impact on SRAM,” Microelectronics Journal, vol. 43, pp. 300–304 (2012)

[24] A. Bindal and S. Hamedi-Hagh , “Silicon nano-wire transistors and their applications for the future of VLSI: an exploratory design study of a 16×16 static random access memory using silicon nanowire transistors,” Journal of Nanoelectronics and Optoelectronics, vol. 2, no. 3, pp. 294–303 (2007)

[25] H. Na , T. Endoh , “A compact half select disturb free static random access memory cell with stacked vertical metal–oxide–semiconductor field-effect transistor,” Japanese Journal of Applied Physics, vol. 51, pp. 02BD03.1–8 (2012)

[32] Y. Sun , H.Y. Yu , N. Singh , K.C. Leong , G.Q. Lo , D.L. Kwong , “Junctionless vertical-Si-nanowire-channel-based SONOS memory with 2-bit storage per cell,” IEEE Electron Device Letters, vol. 32, no. 6, pp. 725–727 (2011)

[35] B. Prince , Vertical 3D Memory Technologies, Wiley (2014)

[36] A. Vandooren , J.P. Colinge , D. Flandre , “Gate-all-around OTA's for rad-hard and high-temperature analog applications,” IEEE Transactions on Nuclear Science, vol. 46, no. 4, pp. 1242–1249 (1999)

[37] J.P. Colinge , Silicon-on-Insulator Technology: Materials to VLSI, edn., Springer, p. 182 and pp. 299–231 (2004)

[39] S. Shin , I.M. Kang , K.R. Kim , “Extraction method for substrate-related components of vertical junctionless silicon nanowire field-effect transistors and its verification on radio frequency characteristics,” Japanese Journal of Applied Physics, vol. 51, pp. 06FE20/1–7 (2012)

[41] R.T. Doria et al., “Junctionless multiple-gate transistors for analog applications,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2511–2519 (2011)

[42] M.L.P. Tan et al., “The drain velocity overshoot in an 80 nm metal–oxide–semiconductor field effect transistor,” Journal of Applied Physics, vol. 105, no. 7, pp. 074503–1-7 (2009)

[43] T. Wang , L. Lou , C. Lee , “A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications,” IEEE Electron Device Letters, vol. 34, no. 4, p. 478 (2013)

[44] S. Hamedi-Hagh , A. Bindal , “Spice modeling of silicon nanowire field-effect transistors for high-speed analog integrated circuits,” IEEE Transactions on Nanotechnology, vol. 7, no. 6, pp. 766–775 (2008)

[45] S. Hamedi-Hagh et al., “Design of next generation amplifiers using nanowire FETs,” Journal of Electrical Engineering & Technology, vol. 3, no. 4, pp. 566–570 (2008)

[46] Y. Cui , C.M. Lieber , “Functional nanoscale electronic devices assembled using silicon nanowire building blocks,” Science, vol. 291, no. 5505, pp. 851–853, 2001

[47] Yu Huang et al., “Logic gates and computation from assembled nanowire building blocks,” Science, vol. 294, no. 9, pp. 1313–1317 (2001)

[50] C.A. Moritz , P. Narayanan , C.O. Chui , “Nanoscale application specific integrated circuits,” in Nanoelectronic Circuit Design, N.K. Jha and D. Chen , eds., Springer, pp. 215–275 (2011)

[52] A. Bindal , S. Hamedi-Hagh , “Static NMOS circuits for crossbar architectures using silicon nano-wire technology,” Semiconductor Science and Technology, vol. 22, pp. 54–64 (2007)

[53] F. Vaurette et al., “Confinement-modulated junctionless nanowire transistors for logic circuits,” Nanoscale, vol. 6, pp. 13446–13450 (2014)

[54] H. Yan et al., “Programmable nanowire circuits for nanoprocessors,” Nature, vol. 470, no. 10, pp. 240–244 (2011)

[56] J. Yao et al., “Nanowire nanocomputer as a finite-state machine,” Proceedings of the National Academy of Sciences of the United States of America (PNAS), vol. 111, no. 7, pp. 2431–2435 (2014) DOI: 10.1073/pnas.1323818111

[57] S. Frache , M. Graziano , M. Zamboni , “Nanoarray architectures multilevel simulation,” ACM Journal on Emerging Technologies in Computing Systems, vol. 10, no. 1, pp. 6:2–6:20 (2014)

[60] M. De Marchi et al., “Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs,” IEEE Electron Device Letters, vol. 35, no. 8, pp. 880–882 (2014)

[62] A. Heinzig et al., “Reconfigurable silicon nanowire transistors,” Nano Letters, vol. 12, no. 1, pp. 119–124 (2012)

[63] A. Heinzig et al., “Dually active silicon nanowire transistors and circuits with equal electron and hole transport,” Nano Letters, vol. 13, no. 9, pp. 4176–4181 (2013)

[64] J. Trommer et al., “Elementary aspects for circuit implementation of reconfigurable nanowire transistors,” IEEE Electron Device Letters, vol. 35, no. 1, pp. 141–143 (2014)

[68] H.-C. Chen et al., “Magnetic-composite-modified polycrystalline-silicon nanowire field-effect transistor for vascular endothelial growth factor detection and cancer diagnosis,” Analytical Chemistry, vol. 86, no. 19, pp. 9443–9450 (2014)

[69] M.-Y. Shen , B.-R. Li , Y.-K. Li , “Silicon nanowire field-effect-transistor based biosensors: from sensitive to ultra-sensitive,” Biosensors and Bioelectronics, vol. 60, pp. 101–111 (2014)

[70] M.-Y. Chen , B.-R. Li , Y.-T. Chen , “Silicon nanowire field-effect transistor-based biosensors for biomedical diagnosis and cellular recording investigation,” Nano Today, vol. 6, pp. 131–154 (2011)

[71] Y.M. Georgiev et al., “Fully CMOS-compatible top-down fabrication of sub-50 nm silicon nanowire sensing devices,” Microelectronic Engineering, vol. 118, pp. 47–53 (2014)

[73] E. Stern et al., “Label-free immunodetection with CMOS-compatible semiconducting nanowires,” Nature, vol. 445, pp. 519–522 (2007)

[75] P. Ginet et al., “CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 065008 (2011)

[76] E. Buitrago et al., “The top-down fabrication of a 3D-integrated, fully CMOS-compatible FET biosensor based on vertically stacked SiNWs and FinFETs,” Sensors and Actuators B: Chemical, vol. 193, pp. 400–412 (2014)

[77] X. Zhao et al., “One-dimensional nanostructure field-effect sensors for gas detection,” Sensors, vol. 14, pp. 13999–14020 (2014)

[78] E. Buitrago et al., “Junctionless silicon nanowire transistors for the tunable operation of a highly sensitive, low power sensor,” Sensors and Actuators B, vol. 183, pp. 1–10 (2013)

[79] J.H. Chua et al., “Label-free electrical detection of cardiac biomarker with complementary metal-oxide semiconductor-compatible silicon nanowire sensor arrays,” Analytical Chemistry, vol. 81, pp. 6266–6271 (2009)

[80] J. Lee et al., “Complementary silicon nanowire hydrogen ion sensor with high sensitivity and voltage output,” IEEE Electron Device Letters, vol. 33, no. 12, pp. 1768–1170 (2012)

[81] E. Buitrago et al., “Electrical characterization of high performance, liquid gated vertically stacked SiNW-based 3D FET biosensors,” Sensors and Actuators B: Chemical, vol. 199, pp. 291–300 (2014)

[82] R. Gautam et al., “Numerical model of gate-all-around MOSFET with vacuum gate dielectric for biomolecule detection,” IEEE Electron Device Letters, vol. 33, no. 12, pp. 1756–1758 (2012)

[83] X. Tang et al., “Direct protein detection with a nano-interdigitated array gate MOSFET,” Biosensors and Bioelectronics, vol. 24, pp. 3531–3537 (2009)

[84] P.R. Nair , M.A. Alam , “Design considerations of silicon nanowire biosensors,” IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3400–3408 (2007)

Metrics

Full text views

Total number of HTML views: 0
Total number of PDF views: 948 *
Loading metrics...

Book summary page views

Total views: 1078 *
Loading metrics...

* Views captured on Cambridge Core between September 2016 - 25th September 2017. This data will be updated every 24 hours.