Introduction

The integrated circuit industry has continuously enjoyed enormous success owing to its ever increasing large-scale integration. With the advent of system-on-a-chip (SOC) technology [30,133], it requires heterogeneous integration to support different modules within one single silicon chip such as logic, memory, analog, RF/microwave, FPGA, and MEMS sensor. Such a heterogeneous integration leads to highly non-uniform current distribution across one layer or between any pair of layers. As a result, it is beneficial to design a structured multi-layer and multi-scale power and ground (P/G) grid [11] that is globally irregular and locally regular [115] according to the current density. This results in a heterogeneously structured P/G circuit model in which each subblock can have a different time constant. In addition, the typical extracted P/G grid circuits usually have millions of nodes and large numbers of ports. To ensure power integrity, specialized simulators for structured P/G grids are required to efficiently and accurately analyze the voltage bounce or drop using macro-models.

In [139], internal sources are first eliminated to obtain a macro-model with only external ports. The entire P/G gird is partitioned at and connected by those external ports. Because elimination results in a dense macro-model, [139] applies an additional sparsification procedure that is error-prone and inefficient. In addition, [18,95] proposed localized simulation and design methods based on the locality of the current distribution in most P/G grids with C4-bumps.