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5 - Passive hierarchical model order reduction

Published online by Cambridge University Press:  19 January 2010

Sheldon Tan
Affiliation:
University of California, Riverside
Lei He
Affiliation:
University of California, Los Angeles
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Summary

In this chapter, we focus on passive wideband modeling of RLCM circuits. We propose a new passive wideband reduction and realization framework for general passive high-order RLCM circuits. Our method starts with large RLCM circuits, which are extracted by existing geometry extraction tools like FastCap [83] and FastHenry [59] under some relaxation conditions of the full-wave Maxwell equations (like electro-quasi-static for FastCap or magneto-quasi-static for FastHenry) instead of measured or simulated data. It is our ultimate goal that we can obtain the compact models directly from complex interconnect geometry without measurement or full-wave simulations. The method presented in this chapter is called hierarchical model order reduction, HMOR, which is based on the general frequency-domain hierarchical model reduction algorithm [121, 122, 124] and an improved VPEC (vector potential equivalent circuit) [134] model for self and mutual inductance, which can be easily sparsified and is hierarchical-reduction friendly.

The HMOR method achieves passive wideband modeling of RLC circuits via multi-point expension and the convex programming based passivity enforcement method. In this section, we will show that the frequency-domain hierarchical reduction is equivalent to implicit moment-matching around s = 0, and that the existing hierarchical reduction method by one-point expansion [121, 124] is numerically stable for general tree-structured circuits.

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Publisher: Cambridge University Press
Print publication year: 2007

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  • Passive hierarchical model order reduction
  • Sheldon Tan, University of California, Riverside, Lei He, University of California, Los Angeles
  • Book: Advanced Model Order Reduction Techniques in VLSI Design
  • Online publication: 19 January 2010
  • Chapter DOI: https://doi.org/10.1017/CBO9780511541117.006
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  • Passive hierarchical model order reduction
  • Sheldon Tan, University of California, Riverside, Lei He, University of California, Los Angeles
  • Book: Advanced Model Order Reduction Techniques in VLSI Design
  • Online publication: 19 January 2010
  • Chapter DOI: https://doi.org/10.1017/CBO9780511541117.006
Available formats
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To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

  • Passive hierarchical model order reduction
  • Sheldon Tan, University of California, Riverside, Lei He, University of California, Los Angeles
  • Book: Advanced Model Order Reduction Techniques in VLSI Design
  • Online publication: 19 January 2010
  • Chapter DOI: https://doi.org/10.1017/CBO9780511541117.006
Available formats
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