Book contents
- Parallel Computer Organization and Design
- Parallel Computer Organization and Design
- Copyright page
- Contents
- Preface
- Commemoration
- Acknowledgments
- 1 Introduction
- 2 Processor Microarchitecture
- 3 Memory Hierarchies
- 4 Multiprocessor Systems
- 5 Coherence, Synchronization, and Memory Consistency
- 6 Chip Multiprocessors
- 7 Quantitative Evaluations
- 8 Graphics Processing Units
- Book part
- Index
7 - Quantitative Evaluations
Published online by Cambridge University Press: aN Invalid Date NaN
Book contents
- Parallel Computer Organization and Design
- Parallel Computer Organization and Design
- Copyright page
- Contents
- Preface
- Commemoration
- Acknowledgments
- 1 Introduction
- 2 Processor Microarchitecture
- 3 Memory Hierarchies
- 4 Multiprocessor Systems
- 5 Coherence, Synchronization, and Memory Consistency
- 6 Chip Multiprocessors
- 7 Quantitative Evaluations
- 8 Graphics Processing Units
- Book part
- Index
Summary
This chapter is dedicated to the correct and reliable communication of values in shared-memory multiprocessors. Correctness properties of the memory system of shared-memory multiprocessors include coherence, the memory consistency model, and the reliable execution of synchronization primitives. Since CMPs are designed as shared-memory multi-core systems, this chapter targets correctness issues not only in symmetric multiprocessors (SMPs) or large-scale cache coherent distributed shared-memory systems, but also in CMPs with core multi-threading. The chapter reviews the hardware components of a shared-memory architecture and why memory correctness properties are so hard to enforce in modern shared-memory multiprocessor systems. We then treat various levels of coherence and the difference between plain memory coherence and store atomicity. We introduce memory models and sequential consistency, the most fundamental memory model, enforcing sequential consistency by store synchronization. Finally, we review thread synchronization and ISA-level synchronization primitives and relaxed memory models based on hardware efficiency and relaxed memory models relying on synchronization.
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- Parallel Computer Organization and Design , pp. 429 - 460Publisher: Cambridge University PressPrint publication year: 2025
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