2 - ThruChip Interface
A Wireless Chip Interface
Published online by Cambridge University Press: 17 September 2021
Summary
Chapter 2 provides an in-depth and intuitive description of TCI, starting with its basic structure and fundamental operating principle. It explains how the transceiver and inductive coupling coils are designed, their electrical characteristics, and design variations. This is followed by an intuitive explanation of how to do design trade-offs to optimize for different performance requirements, with particular emphasis on design options for optimal power and area efficiency respectively. Integration options – 2/2.5/2.9/3D – are also presented to illustrate implementation flexibility. Two power delivery solutions are then introduced, one using wireless and the other advanced doping technologies. Next, three application examples are described, providing insight into how TCI can be adopted and adapted and quantifying performance improvement against conventional wideband DRAM, stacked flash memory, and network-on-chip solutions. Specific challenges in each of the application areas are elaborated and how TCI can be adapted to address these challenges is explained. The chapter concludes with two postscripts. The first introduces a sample of TCI research carried out in other institutions in parallel to our effort. The second provides an overview of collective synchronization, which is utilized to create a low-cost clock distribution solution for TCI.
Keywords
Information
- Type
- Chapter
- Information
- Publisher: Cambridge University PressPrint publication year: 2021
References
Saito, M., Sugimori, Y., Kohama, Y., Yoshida, Y., Miura, N., Ishikuro, H., and Kuroda, T., “47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking,” 2009 IEEE Custom Integrated Circuits Conference, pp. 449–452, Sep. 2009.CrossRefGoogle Scholar
Miura, N., Sakurai, T., and Kuroda, T.. (2007, Feb.). Crosstalk countermeasures for high-density inductive-coupling channel array. IEEE Journal of Solid-State Circuits. 42(2), pp. 410–421.Google Scholar
Miura, N., “積層チップ間誘導結合通信の高密度高速化に関する研究 [High density, high speed inductive coupling interface for 3D chip integration],” in Japanese, Ph.D. dissertation, Dept. of Electronics and Electrical Engineering, Keio Univ., Yokohama, Kanagawa Prefecture, Japan, 2007.Google Scholar
Niitsu, K., Sugimori, Y., Kohama, Y., Osada, K., Irie, N., Ishikuro, H., and Kuroda, T., “Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link,” 2007 IEEE Asian Solid-State Circuits Conference, pp. 131–134, Nov. 2007.Google Scholar
Japan Ministry of Internal Affairs and Communications. (1990, Jun.). 電波防護指針 [Radio radiation protection guidelines]. In Japanese. [Online]. Available: www.tele.soumu.go.jp/resource/j/material/dwn/guide38.pdfGoogle Scholar
Miura, N., Mizoguchi, D., Inoue, M., Niitsu, K., Nakagawa, Y., Tago, M., Fukaishi, M., Sakurai, T., and Kuroda, T.. (2007, Jan.). A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link. IEEE Journal of Solid-State Circuits. 42(1), pp. 111–122.Google Scholar
Miyata, T., “誘導結合を用いた三次元積層SRAM間無線通信 [An inductive-coupling wireless interface between 3D-stacked SRAM module],” in Japanese, Master’s degree dissertation, Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa Prefecture, Japan, 2018.Google Scholar
Saito, M., Miura, N., and Kuroda, T., “Asynchronous pulse transmitter for power reduction in ThruChip Interface,” 2011 International Conference on Solid State Devices and Materials, pp. 1075–1076, Sep. 2011.Google Scholar
Miura, N., Kohama, Y., Sugimori, Y., Ishikuro, H., Sakurai, T., and Kuroda, T.. (2009, Mar.). A high-speed inductive-coupling link with burst transmission. IEEE Journal of Solid-State Circuits. 44(3), pp. 947–955.Google Scholar
Take, Y., Miura, N., and Kuroda, T.. (2011, Nov.). A 30Gb/s/link 2.2Tb/s/mm2 inductively-coupled injection-locking CDR. IEEE Journal of Solid-State Circuits. 46(11), pp. 2552–2559.Google Scholar
Junaidi, A. R., Take, Y., and Kuroda, T., “A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package,” 2014 Symposium on VLSI Circuits, pp. 29–30, Jun. 2014.Google Scholar
Kumagai, K., Yang, C., Izumino, H., Narita, N., Shinjo, K., Iwashita, S., Nakaoka, Y., Kawamura, T., Komabashiri, H., Minato, T., Ambo, A., Suzuki, T., Liu, Z., Song, Y., Goto, S., Ikenaga, T., Mabuchi, Y., and Yoshida, K., “System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV,” 2006 IEEE International Solid State Circuits Conference, pp. 430–431, Feb. 2006.Google Scholar
Lin, C. C., Chen, J. W., Chang, H. C., Yang, Y. C., Yang, Y. H. O., Tsai, M. C., Guo, J. I., and Wang, J. S.. (2007, Jan.). A 160K gates/4.5 KB SRAM H.264 video decoder for HDTV applications. IEEE Journal of Solid-State Circuits. 42(1), pp. 170–182.CrossRefGoogle Scholar
Miura, N., Mizoguchi, D., Inoue, M., Niitsu, K., Nakagawa, Y., Tago, M., Fukaishi, M., Sakurai, T., and Kuroda, T., “A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link,” 2006 IEEE International Solid State Circuits Conference, pp. 424–425, Feb. 2006.CrossRefGoogle Scholar
Miura, N., Ishikuro, H., Niitsu, K., Sakurai, T., and Kuroda, T.. (2008, Jan.). A 0.14pJ/b inductive-coupling transceiver with digitally-controlled precise pulse shaping. IEEE Journal of Solid-State Circuits. 43(1), pp. 285–291.Google Scholar
Miura, N., Ishikuro, H., Sakurai, T., and Kuroda, T., “A 0.14pJ/b inductive-coupling inter-chip data transceiver with digitally-controlled precise pulse shaping,” 2007 IEEE International Solid-State Circuits Conference, pp. 358–359, Feb. 2007.Google Scholar
Ezaki, T., Kondo, K., Ozaki, H., Sasaki, N., Yonernura, H., Kitano, M., Tanaka, S., and Hirayarna, T., “A 160 Gb/s interface design configuration for multichip LSI,” 2004 IEEE International Solid-State Circuits Conference, pp. 140–141, Feb. 2004.Google Scholar
Fazzi, A., Canegallo, R., Ciccarelli, L., Magagni, L., Natali, F., Jung, E., Rolandi, P. L., and Guerrieri, R., “3D capacitive interconnections with mono- and bi-directional capabilities,” 2007 IEEE International Solid-State Circuits Conference, pp. 356–357, Feb. 2007.CrossRefGoogle Scholar
Miura, N., Kohama, Y., Sugimori, Y., Ishikuro, H., Sakurai, T., and Kuroda, T., “An 11Gb/s inductive-coupling link with burst transmission,” 2008 IEEE International Solid-State Circuits Conference, pp. 298–299, Feb. 2008.CrossRefGoogle Scholar
Kim, J. S., Oh, C. S., Lee, H., Lee, D., Hwang, H. R., Hwang, S., Na, B., Moon, J., Kim, J. G., Park, H., Ryu, J. W., Park, K., Kang, S. K., Kim, S. Y., Kim, H., Bang, J. M., Cho, H., Jang, M., Han, C., Lee, J. B., Kyung, K., Choi, J. S., and Jun, Y. H., “A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking,” 2011 IEEE International Solid-State Circuits Conference, pp. 496–498, Feb. 2011,.Google Scholar
Osada, K., Saen, M., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Irie, N., Hattori, T., Hasegawa, A., and Kuroda, T., “3D system integration of processor and multi-stacked SRAMs by using inductive-coupling links,” 2009 Symposium on VLSI Circuits, pp. 256–257, Jun. 2009.Google Scholar
Kawai, S., Ishikuro, H., and Kuroda, T., “A 4.7Gb/s inductive coupling interposer with dual mode modem,” 2009 Symposium on VLSI Circuits, pp. 92–93, Jun. 2009.Google Scholar
Cheng, C., Shiba, K., Hamada, M., and Kuroda, T., “2.5D integration using inductive-coupling TSV-less miniature interposer achieving 317Gb/s/mm2, 1.2pJ/b data transfer,” 2019 International Conference on Solid State Devices and Materials, pp. 517–518, Sep. 2019.CrossRefGoogle Scholar
Poulton, J., Dally, W. J., Chen, X., Eyles, J .G., Greer, T. H., Tell, S. G., and Gray, C. T., “A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications,” 2013 IEEE International Solid-State Circuits Conference, pp. 404–405, Feb. 2013.Google Scholar
Shokrollahi, A., Carnelli, D., Fox, J., Hofstra, K., Holden, B., Hormati, A., Hunt, P., Johnston, M., Keay, J., Pesenti, S., Simpson, R., Stauffer, D., Stewart, A., Surace, G., Tajalli, A., Amiri, O. T., Tschank, A., Ulrich, R., Walter, C., Licciardello, F., Mogentale, Y., and Singh, A., “A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to12mm for MCM packages in 28nm CMOS,” 2016 IEEE International Solid-State Circuits Conference, pp. 182–183, Feb. 2016.Google Scholar
Dickson, T. O., Liu, Y., Rylov, S. V., Dang, B., Tsang, C. K., Andry, P. S., Bulzacchelli, J. F., Ainspan, H. A., Gu, X., Turlapati, L., Beakes, M. P., Parker, B. D., Knickerbocker, J. U., and Friedman, D. J., “An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects,” 2011 Symposium on VLSI Circuits, pp. 80–81, Jun. 2011.Google Scholar
Lin, M. S., Tsai, C. C., Chang, C. H., Huang, W. H., Hsu, Y. Y., Yang, S. C., Fu, C. M., Chou, M. H., Huang, T. C., Chen, C. F., Huang, T. C., Adham, S., Wang, M. J., Shen, W. W., and Mehta, A., “An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application,” 2013 Symposium on VLSI Circuits, pp. 16–17, Jun. 2013.Google Scholar
Dehlaghi, B., and Carusone, A. C., “A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS,” 2015 IEEE Custom Integrated Circuits Conference, pp. 25.1.1–25.1.4, Sep. 2015.Google Scholar
Shiba, K., Cheng, C., Hamada, M., and Kuroda, T.. (2020, Feb.). 2.5D integration using inductive-coupling TSV-less miniature interposer achieving 317 Gb/s/mm2, 1.2 pJ/b data-transfer. Japanese Journal of Applied Physics. 59(SGGL06), pp. 1–6.Google Scholar
Hasegawa, S., Kadomoto, J., Kosuge, A., and Kuroda, T., “A 1 Tb/s/mm2 inductive-coupling side-by-side chip link,” 42nd European Solid-State Circuits Conference, pp. 469–472, Sep. 2016.Google Scholar
Kumagai, M., Uchiyama, N., Ohmura, E., Sugiura, R., Atsumi, K., and Fukumitsu, K., “Advanced dicing technology for semiconductor wafer - Stealth Dicing,” 2006 IEEE International Symposium on Semiconductor Manufacturing, pp. 215–218, Sep. 2006.Google Scholar
Toray. Super high accuracy flip chip bonder OF2000. [Online]. Retrieved on Feb. 3, 2020. Available: www.toray-eng.com/products/semicon/sem_005.htmlGoogle Scholar
Kuroda, T., “Near-field coupling integration technology,” 10th IEEE/ACM International Symposium on Networks-on-Chip, Aug. 2016.Google Scholar
Yuan, Y., Yoshida, Y., and Kuroda, T., “Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS,” 2007 IEEE Asian Solid-State Circuits Conference, pp. 115–118, Nov. 2007.Google Scholar
Onizuka, K., Kawaguchi, H., Takamiya, M., Kuroda, T., and Sakurai, T., “Chip-to-chip inductive wireless power transmission system for SiP applications,” 2006 IEEE Custom Integrated Circuits Conference, pp. 575–578, Sep. 2006.Google Scholar
Ghovanloo, M. and Najafi, K.. (2004, Nov.). Fully integrated wideband high-current rectifiers for inductively powered devices. IEEE Journal of Solid-State Circuits. 39(11), pp. 1976–1984.Google Scholar
Nakamoto, H., Yamazaki, D., Yamamoto, T., Kurata, H., Yamada, S., Mukaida, K., Ninomiya, T., Ohkawa, T., Masui, S., and Gotoh, K., “A passive UHF RFID tag LSI with 36.6% efficiency CMOS-only rectifier and current-mode demodulator in 0.35μm FeRAM technology,” 2006 IEEE International Solid State Circuits Conference, pp. 310–311, Feb. 2006.CrossRefGoogle Scholar
Yuan, Y., Yoshida, Y., Yamagishi, N., and Kuroda, T.. (2008, Apr.). Chip-to-chip power delivery by inductive coupling with ripple canceling scheme. Japanese Journal of Applied Physics. 47(4S), pp. 2797–2800. DOI https://doi.org/10.1143/JJAP.47.2797.Google Scholar
Yuan, Y., Radecki, A., Miura, N., Aikawa, I., Take, Y., Ishikuro, H., and Kuroda, T., “Simultaneous 6Gb/s data and 10mW power transmission using nested clover coils for non-contact memory card,” 2010 Symposium on VLSI Circuits, pp. 199–200, Jun. 2010.Google Scholar
Yuan, Y., Miura, N., Imai, S., Ochi, H., and Kuroda, T., “Digital rosetta stone: a sealed permanent memory with inductive-coupling power and data link,” 2009 Symposium on VLSI Circuits, pp. 26–27, Jun. 2009.Google Scholar
Peck, D. S., “Comprehensive model for humidity testing correlation,” 24th International Reliability Physics Symposium, pp. 44–49, Apr. 1986.Google Scholar
Ditzel, D., “Low-cost 3D chip stacking with ThruChip wireless connections,” Hot Chips 26, Aug. 2014.Google Scholar
Shiba, K., Hamada, M., and Kuroda, T., “3D SoC design with TSV-less power supply employing highly doped silicon via,” 2019 International Conference on Solid State Devices and Materials, pp. 515–516, Sep. 2019.Google Scholar
Yang, W. L., Cheng, C. Y., Tsai, M. S., Liu, D. G., and Shieh, M. S.. (2000, May). Retardation in the chemical–mechanical polish of the boron-doped polysilicon and silicon. IEEE Electron Device Letters. 21(5), pp. 218–220.Google Scholar
Ueyoshi, K., Ando, K., Hirose, K., Takamaeda-Yamazaki, S., Kadomoto, J., Miyata, T., Hamada, M., Kuroda, T., and Motomura, M., “QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS,” 2018 IEEE International Solid-State Circuits Conference, pp. 216–217, 2018.CrossRefGoogle Scholar
Shiba, K., Hamada, M., and Kuroda, T.. (2020, Feb.). 3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via. Japanese Journal of Applied Physics. 59(SGGL04), pp. 1–5.CrossRefGoogle Scholar
DISCO Corporation. Introduction of the Gettering DP Wheel. [Online]. Retrieved on Feb. 3, 2020. Available: www.disco.co.jp/eg/solution/apexp/polisher/gettering.html.Google Scholar
Kim, Y. S., Kodama, S., Mizushima, Y., Maeda, N., Kitada, H., Fujimoto, K., Nakamura, T., Suzuki, D., Kawai, A., Arai, K., and Ohba, T., “Ultra thinning down to 4-μm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications,” 2014 Symposium on VLSI Technology, pp. 1–2. Jun. 2014.CrossRefGoogle Scholar
Cho, J. H., Kim, J., Lee, W. Y., Lee, D. U., Kim, T. K., Park, H. B., Jeong, C., Park, M. J., Baek, S. G., Choi, S., Yoon, B. K., Choi, Y. J., Lee, K. Y., Shim, D., Oh, J., Kim, J., and Lee, S. H., “A 1.2V 64Gb 341GB/s HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control,” pp. 208–209, 2018 IEEE International Solid-State Circuits Conference, Feb. 2018.Google Scholar
Sugimori, Y., Kohama, Y., Saito, M., Yoshida, Y., Miura, N., Ishikuro, H., Sakurai, T., and Kuroda, T., “A 2Gb/s 15pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking,” 2009 IEEE International Solid-State Circuits Conference, pp. 244–245, Feb. 2009.Google Scholar
Saito, M., Miura, N., and Kuroda, T., “A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-die NAND-flash memory stacking,” 2010 IEEE International Solid-State Circuits Conference, pp. 440–441, Feb. 2010.Google Scholar
Kuroda, T., “半導体集積回路装置 [Semiconductor Integrated Circuit Device],” Japanese patent application P2009–197669, Aug. 28, 2009.Google Scholar
Miura, N., Take, Y., Saito, M., Yoshida, Y., and Kuroda, T., “A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip Interface with coupled-resonator-based CDR for NAND flash memory stacking,” 2011 IEEE International Solid-State Circuits Conference, pp. 490–492, Feb. 2011.CrossRefGoogle Scholar
Sheibanyrad, A., Petrot, F., and Jantsch, A., Eds. 3D integration for NoC-based SoC architectures. New York: Springer-Verlag, 2010.Google Scholar
Take, Y., Matsutani, H., Sasaki, D., Koibuchi, M., Kuroda, T., and Amano, H.. (2014, Mar.). 3D NoC with inductive-coupling links for building-block SiPs. IEEE Transactions on Computers. 63(3), pp. 748–763.Google Scholar
Abad, P., Puente, V., Prieto, P., and Gregorio, J. A., “Rotary router: an efficient architecture for CMP interconnection networks,” 34th International Symposium on Computer Architecture, pp. 116–125, Jun. 2007.Google Scholar
Puente, V., Beivide, R., Gregorio, J. A., Prellezo, J. M., Duato, J., and Izu, C., “Adaptive bubble router: a design to improve performance in torus networks,” 1999 International Conference on Parallel Processing, pp. 58–67, Sep. 1999.Google Scholar
Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M., and Nakamura, H.. (2013, Nov.). A scalable 3D heterogeneous multicore with an inductive ThruChip Interface. IEEE Micro. 33(6), pp. 6–15.Google Scholar
Jin, H., Frumkin, M., and Yan, J. (1999, Oct.). The OpenMP implementation of NAS parallel benchmarks and its performance. NAS Technical Report NAS-99-011. [Online]. Available: www.nas.nasa.gov/assets/pdf/techreports/1999/nas-99-011.pdf.Google Scholar
Nomura, A., Matsushita, Y., Kadomoto, J., Matsutani, H., Kuroda, T., and Amano, H.. (2018). Escalator network for a 3D chip stack with inductive coupling ThruChip Interface. International Journal of Networking and Computing. 8(1), pp. 124–139.Google Scholar
Tsuchiya, R., Horiuchi, M., Kimura, S., Yamaoka, M., Kawahara, T., Maegawa, S., Ipposhi, T., Ohji, Y., and Matsuoka, H., “Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control,” 2004 IEEE International Electron Devices Meeting, pp. 631–634, Dec. 2004.Google Scholar
Fletcher, B. J., Das, S., and Mak, T., “A high-speed design methodology for inductive coupling links in 3D-ICs,” 2018 Design, Automation & Test in Europe Conference & Exhibition, pp. 497–502, Mar. 2018.Google Scholar
Fletcher, B. J., Das, S., and Mak, T.. (2019, Mar.). Design and optimization of inductive-coupling links for 3-D-ICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27(3), pp. 711–723.Google Scholar
Long, J. R. and Copeland, M. A.. (1997, Mar.). The modeling, characterization, and design of monolithic inductors for silicon RF IC’s. IEEE Journal of Solid-State Circuits. 32(3), pp. 357–369.CrossRefGoogle Scholar
Fletcher, B. J., Das, S., Poon, C. S., and Mak, T., “Low-power 3D integration using inductive coupling links for neurotechnology applications,” 2018 Design, Automation & Test in Europe Conference & Exhibition, pp. 1211–1216, Mar. 2018.Google Scholar
Stanslaski, S., Afshar, P., Cong, P., Giftakis, J., Stypulkowski, P., Carlson, D., Linde, D., Ullestad, D., Avestruz, A. T., and Denison, T.. (2012, Jan.). Design and validation of a fully implantable, chronic, closed-loop neuromodulation device with concurrent sensing and stimulation. IEEE Transactions on Neural Systems and Rehabilitation Engineering. 20(4), pp. 410–421.Google Scholar
Papistas, I. A. and Pavlidis, V. F., “Contactless inter-tier communication for heterogeneous 3-D ICs,” 2017 IEEE International Symposium on Circuits and Systems, pp. 2585–2588, May 2017.Google Scholar
Kuroda, T.. (2011, Jun.). 自然界の集団同期現象をエレクトロニクスに応用 [Applying nature’s collective synchronization phenomena to electronics]. In Japanese. Nikkei Electronics (2011.6.13). pp. 85–94.Google Scholar
Spontaneous Synchronization. [Online]. Retrieved on Feb. 3, 2020. Available: www.youtube.com/watch?v=RMVxVbCIPjg.Google Scholar
Peskin, C.. Mathematica Aspects of Heart Physiology. New York: Courant Institute of Mathematical Sciences, 1975, pp. 268–278.Google Scholar
Winfree, A.. The Geometry of Biological Time. New York: Springer-Verlag, 1980.CrossRefGoogle Scholar
Kuramoto, Y., “Self-entrainment of a population of coupled nonlinear oscillators,” International Symposium on Mathematical Problems in Theoretical Physics, pp. 420–422, 1975.Google Scholar
Mirollo, R. E. and Strogatz, S. H.. (1990, Dec.). Synchronization of pulse-coupled biological oscillators. SIAM Journal on Applied Mathematics. 50(6), pp. 1645–1662.Google Scholar
Watts, D. and Strogatz, S. H.. (1998, Jun. 4). Collective dynamics of “small-world” networks. Nature. 393, pp. 440–442.Google Scholar
Buchanan, M.. NEXUS: Small Worlds and the Ground-Breaking Science of Networks. New York: W. W. Norton & Co., 2002.Google Scholar
Adler, R., “A study of locking phenomena in oscillators,” Proceedings of the IEEE, pp. 1380–1385, Oct. 1973.Google Scholar
Razavi, B., “Mutual injection pulling between oscillators,” 2006 IEEE Custom Integrated Circuits Conference, pp. 675–678, Sep. 2006.Google Scholar
Shibasaki, T., Tamura, H., Kanda, K., Yamaguchi, H., Ogawa, J., and Kuroda, T.. (2007). 18-GHz clock distribution using a coupled VCO array. IEICE Transactions on Electronics. E90-C(4), pp. 811–822.CrossRefGoogle Scholar
Accessibility standard: Unknown
Why this information is here
This section outlines the accessibility features of this content - including support for screen readers, full keyboard navigation and high-contrast display options. This may not be relevant for you.Accessibility Information
Accessibility compliance for the HTML of this chapter is currently unknown
and may be updated in the future.