Crossref Citations
This Book has been
cited by the following publications. This list is generated based on data provided by Crossref.
Studer, C.
Blosch, P.
Friedli, P.
and
Burg, A.
2007.
Matrix Decomposition Architecture for MIMO Systems: Design and Implementation Trade-offs.
p.
1986.
Shubin, V. V.
2010.
Specific features of constructional optimization of the parameters of CMOS memory devices.
Russian Microelectronics,
Vol. 39,
Issue. 4,
p.
281.
Henzen, Luca
Gendotti, Pietro
Guillet, Patrice
Pargaetzi, Enrico
Zoller, Martin
and
Gürkaynak, Frank K.
2010.
Cryptographic Hardware and Embedded Systems, CHES 2010.
Vol. 6225,
Issue. ,
p.
248.
Trichina, Elena
and
Korkikyan, Roman
2010.
Multi Fault Laser Attacks on Protected CRT-RSA.
p.
75.
Samochin, Alexander
2010.
Optimized hardware architecture for object recognition and tracking.
Optical Engineering,
Vol. 49,
Issue. 10,
p.
107001.
Meinerzhagen, P.
Roth, C.
and
Burg, A.
2010.
Towards generic low-power area-efficient standard cell based memory architectures.
p.
129.
Seethaler, Dominik
and
Bolcskei, Helmut
2010.
Performance and Complexity Analysis of Infinity-Norm Sphere-Decoding.
IEEE Transactions on Information Theory,
Vol. 56,
Issue. 3,
p.
1085.
Bumbăcea, P
Codreanu, V
Hobincu, R
Petrică, L
and
Ştefan, G M
2010.
Technology driven architecture for integral parallel embedded computing.
p.
35.
Novak, Clemens
Studer, Christoph
Burg, Andreas
and
Matz, Gerald
2010.
The effect of unreliable LLR storage on the performance of MIMO-BICM.
p.
736.
Shubin, Vladimir V.
2010.
New high-speed CMOS full adder cell of mirror design style.
p.
128.
Greisen, Pierre
Haene, Simon
and
Burg, Andreas
2010.
Simulation and Emulation of MIMO Wireless Baseband Transceivers.
EURASIP Journal on Wireless Communications and Networking,
Vol. 2010,
Issue. 1,
Shubin, V. V.
2011.
New CMOS circuit implementation of a one-bit full-adder cell.
Russian Microelectronics,
Vol. 40,
Issue. 2,
p.
119.
Kahng, Andrew B.
Lienig, Jens
Markov, Igor L.
and
Hu, Jin
2011.
VLSI Physical Design: From Graph Partitioning to Timing Closure.
p.
1.
Gimenez, Salvador Pinillos
Alati, Daniel Manha
Simoen, Eddy
and
Claeys, Cor
2011.
FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs.
Journal of The Electrochemical Society,
Vol. 158,
Issue. 12,
p.
H1258.
Sato, Norio
Sato, Yasuhiro
Kado, Yuichi
Ciappa, Mauro
Aemmer, Dölf
Kaeslin, Hubert
and
Fichtner, Wolfgang
2011.
A Multilevel CMOS–MEMS Design Methodology Based on Response Surface Models.
Journal of Microelectromechanical Systems,
Vol. 20,
Issue. 3,
p.
609.
Hari, Om Prakash
and
Mai, Ashis Kumar
2011.
Low power and area efficient implementation of N-phase non overlapping clock generator using GDI technique.
p.
123.
Golubcovs, Stanislavs
and
Yakovlev, Alex
2011.
Low Power Networks-on-Chip.
p.
71.
Meinerzhagen, Pascal Andreas
Andiç, Onur
Treichler, Jürg
and
Burg, Andreas Peter
2011.
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems.
p.
343.
Henzen, Luca
Aumasson, Jean-Philippe
Meier, Willi
and
Phan, Raphael C.-W.
2011.
VLSI Characterization of the Cryptographic Hash Function BLAKE.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
Vol. 19,
Issue. 10,
p.
1746.
Roth, C.
Cevrero, A.
Studer, C.
Leblebici, Y.
and
Burg, A.
2011.
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
p.
1772.