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Plasmonic isolator for photonic integrated circuits

  • Hiromasa Shimizu (a1) and Vadym Zayets (a2)
Abstract

This article discusses recent studies of on-chip integration of a plasmonic isolator on a Si substrate and a hybrid isolator on an InP substrate. The key characteristics of the plasmonic isolator are reviewed and future prospects are discussed. A method to enhance the magneto-optical figure of merit (FOM) and reduce the propagation loss of a surface plasmon in order to realize the proposed design of the plasmonic isolator is described. One hundred percent enhancement of the FOM and 20× reduction of propagation loss in the optimized ferromagnetic plasmonic structure are experimentally demonstrated.

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MRS Bulletin
  • ISSN: 0883-7694
  • EISSN: 1938-1425
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