Hostname: page-component-76fb5796d-2lccl Total loading time: 0 Render date: 2024-04-25T07:20:08.623Z Has data issue: false hasContentIssue false
  • English
  • Français

3D Modelling Of The Novel Nanoscale Screen-Grid FET

Published online by Cambridge University Press:  01 February 2011

Pei W. Ding ,
Kristel Fobelets  and
Jesus E Velazquez-Perez
Pei W. Ding
Affiliation:
pei.ding@ic.ac.ukImperial CollegeDepartment of Electrical EngineeringLondon
Kristel Fobelets
Affiliation:
k.fobelets@ic.ac.uk, Imperial College, Department of Electrical Engineering, London, United Kingdom
Jesus E Velazquez-Perez
Affiliation:
js@usal.es, Universidad de Salamanca, Departamento de Fisica Aplicada, Salamanca, Spain
Get access

Abstract

A novel field effect transistor (FET) that uses 3-dimensional (3-D) embedded gate fingers – the Screen-Grid Field Effect Transistor (SGFET) – is proposed. The gating action of the SGFET is based on the design of multiple gating cylinders into the channel region, perpendicular to the current flow. Such configuration allows a full 3-D gate control of the current which improves the device characteristics by increasing the gate to channel coupling. Initial investigations of the SGFET using 3-D TCAD TaurusTM simulation software are presented in this paper. The results indicate that the proposed SGFET offers the possibility of downscaling without degrading the output characteristics. A comparison between the SGFET and both bulk and SOI MOSFETs shows the superior characteristics of the SGFET for low power operation.

Keywords

devicessimulationnanoscale
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 913: Symposium D – Transistor Scaling – Methods, Materials and Modeling , 2006 , 0913-D05-08
Copyright
Copyright © Materials Research Society 2006

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1 Asai, S. and Wada, Y., Proc. IEEE 85, 505 (1997).Google Scholar
2 Taurus TM . Version X-2005.10, Synopsys, Inc.Google Scholar
3 Bozler, C., Alley, G., IEEE Trans. Electron. Devices ED–27 (6), 1128 (1980).Google Scholar
4 Langdo, T., et al., Solid State Electron. 48 (8), 1357 (2004).Google Scholar
5 Executive Summary Of ITRS, 2005, http://www.itrs.net/Common/2005ITRS/Home2005.Google Scholar
6 Polishchuk, I., and Hu, C., Appl. Phys. Lett. 76 (14), 1938 (2000).Google Scholar
7 Pei, G., et. al., IEEE Trans. Electron. Devices 49 (8), 1411 (2002).Google Scholar