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CMP at the Wafer Edge – Modeling the Interaction between Wafer Edge Geometry and Polish Performance

Published online by Cambridge University Press:  01 February 2011

Xiaolin Xie
Microsystems Technology Laboratories, MIT, 60 Vassar St., Cambridge, MA 02139
Duane Boning
Microsystems Technology Laboratories, MIT, 60 Vassar St., Cambridge, MA 02139
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As the drive to improve integrated circuit manufacturing yield continues, renewed attention is being paid to the edge of the wafer. The industry is seeking to reduce the edge exclusion region and achieve good performance to within 2 mm or smaller. This creates substantial challenges, both for CMP and for the starting wafer. In this work, we consider two key elements that play a role in non-uniform polish near the edge of the wafer.

First, we study the impact of localized pressure on the edge of the wafer as a function of the wafer and retaining ring pressures, gap separation between wafer and retaining ring, and pad material properties (pad Young's modulus). Simulations show that several millimeters into the wafer from the edge can polish either more quickly or more slowly than the center of the wafer, depending on the combination of these parameters. Second, we also consider the impact of wafer edge roll-off (the specific thickness or front surface elevation of the wafer geometry) on polishing uniformity. We again find that the polish uniformity can be affected dramatically, depending on the details of the starting wafer geometry.

We believe that several innovations and optimizations are likely to arise in order to meet future wafer edge polish uniformity requirements. These include tool geometry and process improvements, tailoring of the pad material properties, and starting wafer edge geometry optimization and control.

Research Article
Copyright © Materials Research Society 2005

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