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CMP Modeling and Characterization for Polysilicon MEMS Structures

Published online by Cambridge University Press:  15 March 2011

Brian Tang
Microsystems Technology Laboratories, MIT 60 Vassar St., Bldg. 39-328, Cambridge, MA 02139
Duane Boning
Microsystems Technology Laboratories, MIT 60 Vassar St., Bldg. 39-328, Cambridge, MA 02139
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The current bedrock technology for integrated circuit (IC) planarization, chemical-mechanical polishing is beginning to play an important role in microelectromechnical systems (MEMS). However, MEMS devices operate with bigger feature sizes in comparison to ICs, in order to fulfill mechanical functions. We present an experiment to characterize and model a polysilicon CMP process with the specific goal of examining MEMS-sized test structures. We utilize previously discussed CMP models and examine whether assumptions from IC CMP can be applied to MEMS CMP. An analysis of the data collected points to a polishing dependence on not only pattern density, but also partly on feature size or feature configuration. The existing pattern density and step height CMP models are able to capture the major trends in up and down area polishing. However, certain layout features relevant to MEMS are difficult to predict, motivating the need for further model development and application.

Research Article
Copyright © Materials Research Society 2004

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