Hostname: page-component-6766d58669-bkrcr Total loading time: 0 Render date: 2026-05-19T18:13:57.512Z Has data issue: false hasContentIssue false
  • English
  • Français

A Dimple-Array Interconnect Technique for Power Semiconductor Devices

Published online by Cambridge University Press:  21 March 2011

Simon S. Wen ,
Daniel Huff  and
Guo-Quan Lu
Simon S. Wen
Affiliation:
Power Electronics Packaging Laboratory, Center for Power Electronics Systems, The Bradley Department of Electrical and Computer Engineering, Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA, Phone: 1-540-231-3233, Email: swen@vt.edu
Daniel Huff
Affiliation:
Power Electronics Packaging Laboratory, Center for Power Electronics Systems, The Bradley Department of Electrical and Computer Engineering, Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA, Phone: 1-540-231-3233
Guo-Quan Lu
Affiliation:
Power Electronics Packaging Laboratory, Center for Power Electronics Systems, The Bradley Department of Electrical and Computer Engineering, Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA, Phone: 1-540-231-3233
Get access

Abstract

This paper describes a wireless-bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Electrical connections onto the devices are established by soldering arrays of dimples pre-formed on a metal sheet. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced parasitic noises, improved heat dissipation, as well as lowered processing complexity, compared to the conventional wire bonding technology in power module manufacturing. Thermomechanical analysis using thermal cycling test and FEM were also performed to evaluate the reliability characteristics of this interconnect technique for power devices.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 682: Symposium N – Microelectronics and Microsystems Packaging , 2001 , N5.3
Copyright
Copyright © Materials Research Society 2001

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

1 Temple, Vic, ThinPak Technology Shrinks Power Modules, Power Hybrids and Ultra-High Speed Switching Devices, PCIM, pp. 32-38, May 2000.Google Scholar
2 Fisher, R., Fillion, R., Burgess, J., and Hennessy, W., High Frequency, Low Cost, Power Packaging Using Thin Film Power Overlay Technology, Proceedings of IEEE Applied Power Electronics Conference, pp. 12–17, May, 1995.Google Scholar
3 Ozmat, B., Korman, C. S., McConnelee, P., Kheraluwala, M., Delgado, E. and Fillion, R., New Power Module Packaging for Enhanced Thermal Management, Las Vegas, Nevada, May 2000.Google Scholar
4 Klein, Jon, Bottomless SO-8 Package Boosts MOSFET Performance, PCIM, pp. 110, May 2000.Google Scholar
5 Haque, S., Xing, K, Lu, G-Q., Nelson, D. J., Borojevic, D. and Lee, F.C., “Packaging for Thermal Management of Power Electronics Building Blocks Using Metal Posts Interconnected Parallel Plate Structure”, in Proceedings of the Sixth Intersociety Conference on Thermal and Thermal-mechanical Phenomena in Electronic Systems, 1998.Google Scholar
6 Liang, Zhenxian, Multilayer Integration Technology for Packaging of IPEM, Proceedings of 17th Annual VPEC Seminar, Blacksburg, VA, USA, September 19-21, 1999 Google Scholar
7 Liu, Xingsheng, Jing, Xiukuan, and Lu, Guo-Quan, Chip-scale Packaging of Power Devices and its Application in Integrated Power Electronics Module, Proceedings of IEEE ECTC Conference, pp. 290–296, Las Vegas, NV, May 2000.Google Scholar
8 Wen, Simon and Lu, Guo-Quan, Finite-element Modeling of Thermal and Thermomechanical Behavior for Three-dimensional Packaging of Power Electronics Modules, Proceeding of the 7th Intersociety Conference on Theraml and Thermomechanical Phenomena in Electronic Systems, Vol. II, pp. 303–309, Las Vegas, Nevada, May 23-26, 2000.Google Scholar
9 Hong, Bor Zen, Thermal Fatigue Analysis of a CBGA Package with Leadfree Solder Fillets, InterSociety Conference on Thermal Phenomena, pp. 220–228, Seattle, WA, USA, May 6, 1998.Google Scholar
10 Goldmann, L. S., Geometric Optimization of Controlled Collapse Interconnections, IBM J. Research & Development, v. 13, No. 3, May 1969, pp. 251–265.Google Scholar
11 Satoh, R., Arakawa, K., Harada, M., and Matsui, K., Thermal Fatigue Life of Pb-Sn Alloy Interconnections, IEEE Trans. On CHMT, 14(1), pp.224–232, March 1991.Google Scholar
12 Hong, Bor Zen, and Ray, Sudipta K., Ceramic Column Grid Array Technology with Coated Solder Columns, 2000 Electronic Components and Technology Conference, May 2000, pp. 1347–1353.Google Scholar