Accelerated reliability testing of VLSI layered metallizations involves monitoring the resistance of interconnect test structures under the assumption that changes in the resistance are due to processes (i.e., damage) which are induced by the test conditions (current and/or temperature.) “Failure” of the interconnect is defined as a somewhat arbitrary increase in fractional resistance ΔR/Ro ≈ +10% to +30%, where Ro is the initial resistance. However interpretation of the measured ΔR/Ro (both positive and negative) is complicated by other processes, the test conditions, and the test structure itself which all contribute to ΔR/Ro. We estimate the magnitude of intrinsic factors, such as vacancies and solute effects, as well as extrinsic factors, such as interconnect strain and voiding, on measured on ΔR/Ro. We also show that localized joule heating at voids (a mixed intrinsic + extrinsic effect) principally accounts for the large ΔR/Ro measured during electromigration (i.e., high current) testing. These results suggest improved methods for the detection of interconnect voids induced by the stresses of passivation confinement. We outline the considerations which allow for more rigorous failure criteria which are scalable to any metallization layer scheme, interconnect length and test condition. Finally, we discuss the interpretation of resistance changes at interlevel via structures.