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Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features

Published online by Cambridge University Press:  01 February 2011

Claude Ortolland ,
Pierre Morin ,
Franck Arnaud ,
Stephane Orain ,
Chandra Reddy ,
Catherine Chaton  and
Peter Stolk
Claude Ortolland
Affiliation:
claude.ortolland@philips.com, Philips Semiconductors, Process Integration 65nm, 860, rue Jean Monnet, Crolles, Isere, 38926, France
Pierre Morin
Affiliation:
pierre.morin@st.com, ST Microelectronics, 850, rue Jean Monnet, Crolles, Isere, 38926, France
Franck Arnaud
Affiliation:
franck.arnaud@st.com, ST Microelectronics, 850, rue Jean Monnet, Crolles, Isere, 38926, France
Stephane Orain
Affiliation:
stephane.orain@philips.com, Philips Semiconductors, 860, rue Jean Monnet, Crolles, Isere, 38926, France
Chandra Reddy
Affiliation:
chandra.reddy@freescalecrolles.st.com, Freescale Semiconductor, 870, rue Jean Monnet, Crolles, Isere, 38926, France
Catherine Chaton
Affiliation:
catherine.chaton@st.com, CEA-LETI, 850, rue Jean Monnet, Crolles, Isere, 38926, France
Peter Stolk
Affiliation:
peter.stolk@philips.com, Philips Semiconductors, 860, rue Jean Monnet, Crolles, Isere, 38926, France
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Abstract

In this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: <110> and <100>. This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.

Keywords

devicesnitridefilm

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 913: Symposium D – Transistor Scaling – Methods, Materials and Modeling , 2006 , 0913-D02-02
Copyright
Copyright © Materials Research Society 2006

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References

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