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Performance and Reliability of Scaled Gate Dielectrics

Published online by Cambridge University Press:  10 February 2011

W. M. Paulson ,
P. J. Tobin ,
H-H. Tseng ,
B. Maiti ,
C. Gelatos ,
R. I. Hegde  and
S. G. H. Anderson
W. M. Paulson
Affiliation:
Advanced Products Research and Development Laboratory
P. J. Tobin
Affiliation:
Advanced Products Research and Development Laboratory
H-H. Tseng
Affiliation:
Advanced Products Research and Development Laboratory
B. Maiti
Affiliation:
Advanced Products Research and Development Laboratory
C. Gelatos
Affiliation:
Advanced Products Research and Development Laboratory
R. I. Hegde
Affiliation:
Advanced Products Research and Development Laboratory
S. G. H. Anderson
Affiliation:
Advanced Products Research and Development Laboratory
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Abstract

Gate dielectrics for advanced ULSI circuits are rapidly scaling below 10 nm. Thinner dielectrics and smaller lateral dimensions are essential to produce high performance transistors for memories, microprocessors and microcontrollers. In this overview we will discuss the factors that affect the performance and reliability of scaled gate dielectrics. Process parameters that affect oxide and oxynitride dielectrics include substrates, pre-gate cleaning, growth parameters and growth techniques as well as oxide and oxynitride dielectric materials. Thin dielectrics require new or modified measurement methods and extensive use of physical analysis techniques such as SIMS, XPS, AFM and TEM to characterize these materials. Boron diffusion through thin gate oxides, HCI stress, and process induced damage can degrade dielectric quality and affect long term reliability. These factors will affect the performance and reliability of circuits with scaled gate dielectrics.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 473: Symposium J – Materials Reliability in Microelectronics VII , 1997 , 77
Copyright
Copyright © Materials Research Society 1997

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