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Designing and Building Reliability Into VLSI Interconnect Systems

Published online by Cambridge University Press:  25 February 2011

Carole D. Graas
Affiliation:
Semiconductor Process and Device Center, Texas Instruments Inc., P.O. Box 655012 MS 461, Dallas, Texas 75265.
Qi-Zhong Hong
Affiliation:
Semiconductor Process and Device Center, Texas Instruments Inc., P.O. Box 655012 MS 461, Dallas, Texas 75265.
Larry L Ting
Affiliation:
Semiconductor Process and Device Center, Texas Instruments Inc., P.O. Box 655012 MS 461, Dallas, Texas 75265.
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Abstract

The optimization of electromigration (EM) and stress-induced voiding (SV) properties of advanced interconnects impacts many critical system design parameters. In particular, the choice of materials and manufacturing processes must be carefully planned during the early phases of product development. In layered metallizations, both the barrier and capping layers design can affect electromigration resistance and stress-relaxation behavior, while electrical performance often constitutes a trade-off. This is shown specifically in a study of titanium diffusion into Al-Cu from TiN barrier layers, and in initial stress-relaxation tests characterizing the effect of Ti addition in the capping layer. The development of advanced characterization techniques supports the trial-and-error experimental optimization process, but models predicting EM and SV reliability are needed and should include complex sets of microstructural and design parameters.

Type
Research Article
Copyright
Copyright © Materials Research Society 1994

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References

REFERENCES

1 Thompson, C. V. and Lloyd, J. R., MRS Bulletin, 18 (12), pp. 1925 (1993).CrossRefGoogle Scholar
2 Katto, H. and Shimizu, S. in Reliability of Semiconductor Devices and Interconnections and Multilevel Metallization, Interconnections and Contact Technologies, ECS Proceedings 89 (6), pp. 2637.Google Scholar
3 Sullivan, T. D., Ryan, J. G., Riendeau, J. R. and Bouldin, D. P. in Metallization: Performance and Reliability Issues for VLSI and ULSI, SPIE Proceedings 1596, pp. 8395(1991).Google Scholar
4 Towner, J. M., Dirks, A. G. and Tien, T., IEEE/IRPS Proceedings, pp. 711 (1986).Google Scholar
5 Hosoda, T., Niwa, H., Yagi, H. and Tsuchikawa, H., IEEE/IRPS Proceedings, pp.7783 (1991).Google Scholar