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Development of 3D-Packaging Process Technology for Stacked Memory Chips

  • Toshiro Mitsuhashi (a1), Yoshimi Egawa (a2), Osamu Kato (a3), Yoshihiro Saeki (a4), Hidekazu Kikuchi (a5), Shiro Uchiyama (a6), Kayoko Shibata (a7), Junji Yamada (a8), Masakazu Ishino (a9), Hiroaki Ikeda (a10), Nobuaki Takahashi (a11), Yoichiro Kurita (a12), Masahiro Komuro (a13), Satoshi Matsui (a14) and Masaya Kawano (a15)...

A 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.

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1. Takahashi, Kenji et al., “Process Integration of 3D Chip Stack with Vertical Interconnection” in Proc. 2004Electronic Components and Technology Conference, pp. 601609
2. Garrou, Philip, “3D Integration: A Status Report” in Proc. 3D Architectures for Semiconductor Integration and Packaging, Tempe, Arizona, June, 2005
3. Ikeda, H., Kawano, M. and Mitsuhashi, T., “Stacked Memory Chip Technology Development”, SEMI Technology Symposium (STS) 2005 Proceedings, Session 9 pp. 3742.
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MRS Online Proceedings Library (OPL)
  • ISSN: -
  • EISSN: 1946-4274
  • URL: /core/journals/mrs-online-proceedings-library-archive
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