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The Development of a Direct-Polish Process for STI CMP

Published online by Cambridge University Press:  01 February 2011

Antonella Martin ,
Giulia Spinolo ,
Sonia Morin ,
Maurizio Bacchetta ,
Francesca Frigerio ,
Benjamin A. Bonner ,
Peter McKeever ,
Maurizio Tremolada  and
Anand Iyer
Antonella Martin
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Giulia Spinolo
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Sonia Morin
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Maurizio Bacchetta
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Francesca Frigerio
Affiliation:
ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy
Benjamin A. Bonner
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
Peter McKeever
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
Maurizio Tremolada
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
Anand Iyer
Affiliation:
Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA
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Abstract

The development of a direct polish process for STI CMP on 200mm wafers using highselectivity slurry (HSS) has been achieved for production of 0.13μm technology microelectronic devices. The new process has improved on-wafer performance compared to standard STI CMP processes. The step height range across the wafer was decreased by 84%, planarity Cpk values (silicon nitride thickness and step-height uniformity) were increased by >25%, leakage current statistics were superior, and the cost of ownership was lowered by 78%. Cross-sectional SEMs both after direct polish CMP and after removal of the silicon nitride show improved planarity.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 767: Symposium F – Chemical-Mechanical Planarization , 2003 , F5.10
Copyright
Copyright © Materials Research Society 2003

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