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Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

Published online by Cambridge University Press:  01 February 2011

Nihar R. Mohapatra ,
Madhav P. Desai ,
Siva G. Narendra  and
V. Ramgopal Rao
Nihar R. Mohapatra
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India
Madhav P. Desai
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India
Siva G. Narendra
Affiliation:
Microprocessor Research Lab, Intel Corporation Hillsboro, OR, USA
V. Ramgopal Rao
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India
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Abstract

The impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 716: Symposium B – Silicon Materials-Processing, Characterization, and Reliability , 2002 , B3.3
Copyright
Copyright © Materials Research Society 2002

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