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Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology

Published online by Cambridge University Press:  01 February 2011

Fabrice Jerome Letertre
Fabrice Jerome Letertre*
Affiliation:
fabrice.letertre@soitec.fr, Soitec SA, R&D, Parc technologique des Fontaines, Bernin, 38190, France, +33476927665, +33476929431
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Abstract

Engineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors' current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond [1] technologies.

The Smart Cutä technology, introduced in the mid 1990's by M. Bruel [2] is a revolutionnary and powerful thin film technology for bringing to industrial maturity engineered substrate solutions. It is a combination of wafer bonding and layer transfer via the use of ion implantation. It allows multiple high quality transfers of thin layers, from a single crystal donor wafer onto another substrate of a different nature, allowing the integration of dissimilar materials. As a consequence, it opens the path to the formation of III-V based engineered substrates by integrating, for example, materials like GaAs [3], InP [4], SiC [5], GaN [6], Germanium [7] ,and Si [8 ]on a silicon, poly SiC, sapphire, ceramic, or metal substrates?

In this paper, we will review the current wafer bonding and layer transfer technologies with a special emphasis on the Smart Cut technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering will be illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing [9,10,11,12] as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/ optoelectronics functions hybrid integration [13, 14]. Recent results obtained in these two focused areas will be presented to emphasize the added functionalities offered by engineered substrates.

[1] B. Ghyselen et al., ICSI3 proc., 173 5 (2003)

[2] M. Bruel et al., Electron. Lett., vol 31, p. 1201 (1995)

[3] E. Jalaguier et al., Electron. Lett., 34(4), 408 (1998)

[4] E. Jalaguier et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999)

[5] L. Di Cioccio et al., Mat. Sci. and Eng. B Vol. 46, p. 349 (1997)

[6] A. Tauzin and al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119-127

[7] F. Letertre, et al. MRS Symp. Proc., 809, B4.4 (2004).

[8] B. Faure et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106-118

[9] H. Larèche et al., Mat. Sci. For., Vols. 457–460 pp.. 1621 – 1624 (2004)

[10] G. Meneghesso et al , IEDM 2007, to be published

[11] Y. Dikme et al., Journal of Crystal Growth, v.272 (1-4), pp. 500-505 (2004)

[12] J. Dorsaz and al., Proceedings, ICNS6 (2005)

[13] S.G. Thomas et al., IEEE EDL Vol. 26, July 2005.

[14] K. Chilukuri, Semi. Sci. Technol. 22 (2007) 29-34

Keywords

semiconductingbondingIII-V
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1068: Symposium C – Advances in GaN, GaAs, SiC and Related Alloys on Silicon Substrates , 2008 , 1068-C01-01
Copyright
Copyright © Materials Research Society 2008

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References

REFERENCES

1. Shimbo, M. et al. JAP, 60, 2987 (1986)Google Scholar
2. Lasky, J.B, APL, 48, 78 (1986)Google Scholar
3. Blackstone, S. Conference proceedings, Vol. 95-7, 1995, p. 56 Google Scholar
4. Abe, T. et al. , Conference Proceedings, Vol. 92-7, ECS 1992, P. 200 Google Scholar
5. Seidel, H et al. Journal of ECS, 137, 3626 (1990)Google Scholar
6. Godbey, D. et al. , APL, 56, 373 (1990)Google Scholar
7. Lehmann, V. et al. , Journal of ECS, 138, L3 (1984)Google Scholar
8. Yablonovitch, E. et al. , APL, 56, 2419 (1990)Google Scholar
9. Klem, J.F et al. , JAP, 66, 459 (1989)Google Scholar
10. Wada, H. et al. , conference proceedings, Vol. 95-7, 1995, p. 579 Google Scholar
11. Bruel, M. et al. , Electron. Lett., vol 31, p. 1201 (1995)Google Scholar
12. Auberton-Hervé, A.J. and Maleville, C. IEEE Int. SOI Conf., p. 1 (2002).Google Scholar
13. Jalaguier, E. et al. , Electron. Lett., 34(4), 408 (1998)Google Scholar
14. Jalaguier, E. et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999)Google Scholar
15. Cioccio, L. Di et al. , Mat. Sci. and Eng. B Vol. 46, p. 349 (1997)Google Scholar
16. Tauzin, A. and et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119–127 Google Scholar
17. Letertre, F. et al. MRS Symp. Proc., 809, B4.4 (2004).Google Scholar
18. Faure, B. et al. , Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106–118 Google Scholar
19. Cioccio, L. Di et al. , Mat. Sci. and Eng. B Vol. 46, p. 349 (1997)Google Scholar
20. Tong, Q.Y. Gösele, U., Advanced Materials, 11, pp. 1409–1425 (1999).Google Scholar
21. Grisolia, J. MRS spring meeting proceedings, C3 (1999)Google Scholar
22. Personnic, S. et al. , JAP 103, 023508 (2008)Google Scholar
23. Letertre, F. et al. phys. stat. sol. (c) 0 (7), pp. 2103–2106 (2003)Google Scholar
24. Lahrèche, H. et al. , Mat. Sci. For., Vols. 457–460 pp.. 1621–1624 (2004)Google Scholar
25. Dikme, Y. et al. , Journal of Crystal Growth, v. 272 (1-4), pp. 500–505 (2004)Google Scholar
26. Fieger, M. and et al., phys. stat. sol. (c), 2 (7), pp. 2607–2610 (2005)Google Scholar
27. Meneghesso, G. et al. , IEDM 2007, to be publishedGoogle Scholar
28. Hoel, V. et al. , Electronics Letters, 31st of january 2008, Vol. 44, N°3Google Scholar
29. Dorsaz, J. and et al., Proceedings, ICNS6 (2005)Google Scholar
30. Hudait, M.K. et al. , pp. 625–628, IEDM 2007 Google Scholar
31. Kim, DH et al. , pp. 629–632, IEDM 2007 Google Scholar
32. Dohrman, C.L. et al. , Materials Science and Engineering B (135) 235–237 Google Scholar
33. Fitzgerald, E.A. et al. , APL 59, 93 (1991) 811Google Scholar
34. Letertre, F. et al. , Mat. Res. Soc. Proc. 809, B4.4, p.153 (2004)Google Scholar
35. Deguet, C. et al. , ECS Proc., Vol.2005-06 (2005)Google Scholar
36. Akatsu, et al. , APL 86, 181910 (2005)Google Scholar
37. Thomas, S.G. et al. , IEEE EDL Vol. 26, July 2005.Google Scholar
38. Herrick, K.J. MRS spring meeting 2008, symposium C, to be publishedGoogle Scholar