Hostname: page-component-cb9f654ff-d5ftd Total loading time: 0 Render date: 2025-09-11T03:17:46.468Z Has data issue: false hasContentIssue false
  • English
  • Français

Formation of Shallow P+ Junctions Using Two-StepAnneals

Published online by Cambridge University Press:  25 February 2011

C.I. Drowley ,
J. Adkisson ,
D. Peters  and
S.-Y. Chiang
C.I. Drowley
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
J. Adkisson
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304 >Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139
D. Peters
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
S.-Y. Chiang
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
Get access

Abstract

Shallow (0.15-0.2 μm deep) p+ junctions have been formed using boronimplanted into silicon which was pre-amorphized using a silicon implant. Theimplants were annealed using a two-step process; initially the wafers werefurnace annealed at 600 °C for 100 min., followed by a rapid isothermalanneal (RIA) at 950-1100 °C for 10 sec. For comparison, some wafers wereonly given a single-step rapid isothermal anneal at 950-1100 °C for 10 sec.The shallowest junctions were formed when the amorphous silicon layer wasdeeper than the boron implant, because of the suppression of channelling.When the amorphous/crystalline interface was shallower than the tail of theboron implant, some channeling occurred. This channeling tail exhibited anenhanced diffusion during the single-step RIA which was reducedsignificantly by the two-step anneal. When the amorphous layer was deeperthan the boron implant, the single-step and two-step anneals gave identicalresults.

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

1. Seidel, T.E. IEEE Electron Dev. Lett. EDL–4, 353 (1983)Google Scholar
2. Seidel, T.E., Knoell, R., Stevie, F.A., Poli, G., and Schwartz, B., in VLSI Science and Technology/1984, ed. by Bean, K.E. and Rozgonyi, G.A. (Electrochemical Society, Pennington, NJ, 1984) 201Google Scholar
3. Yamada, K., Kashiwagi, M., and Taniguchi, K., Proc. 14th Conf. (1982 International) on Solid State Devices, Jap. J. Appl. Phys. 22, Suppl. 22-1, 157 (1983)Google Scholar
4. Sedgwick, T.O., Kalish, R., Mader, S.R., and Shatas, S.C., Mat. Res. Soc. Symp. Proc. 23, 293 (1984)Google Scholar
5. Sedgwick, T.O., Cohen, S.A., Oehrlein, G.S., Deline, V.R., Kalish, R., and Shatas, S., in VLSI Science and Technology/1984, ed. by Bean, K.E. and Rozgonyi, G.A., (Electrochemical Society, Pennington, NJ, 1984) 192 Google Scholar
6. Hodgson, R.T., Deline, V., Mader, S.M., Morehead, F.F., and Gelpey, J., Mat. Res. Soc. Symp. Proc. 23, 253 (1984)Google Scholar
7. Fair, R.B., Wortman, J.J, and Liu, J., International Electron Dev. Meeting Tech. Digest (IEEE, New York, 1983) 658 Google Scholar
8. Gat, A., AG Associates, private communication. See also ref. [5].Google Scholar
9. The SIMS measurements were performed at Charles Evans Associates.Google Scholar
10. Fair, R.B., Electrochem, J.. Soc. 122, 800 (1975)Google Scholar
11. McMillan, G.B., Shannon, J.M., and Ahmed, H., IEEE Electron Dev. Lett. EDL–5, 280 (1984)Google Scholar