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Influence of Embedded a-Si:H Layer Location on Floating-gate a-Si:H TFT Memory Functions

  • Yue Kuo (a1) and Mary Coan (a2)

The influence of the location of the embedded a-Si:H layer in the gate dielectric film of the floating-gate a-Si:H TFT on the charge trapping and detrapping mechanisms has been investigated. The thin channel-contact SiNx gate dielectric layer favors both hole and electron trappings under the proper gate voltage condition. The sweep gate voltage affect the locations and shapes of forward and backward transfer characteristics curves, which determines the memory function. In order to achieve a large memory window, both the location of the embedded a-Si:H layer and the gate voltage sweep range need to be optimized.

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1 Y. Kuo and H. Nominanda , Appl. Phys. Lett. 89, 1 (2006).

2 Y. Kuo and H. Nominanda , Mat. Res. Soc. Symp. Proc. Vol. 989, Warrendale, PA, A1003 (2007).

3 Y. Kuo and H. Nominanda , J. Korean Phys. Soc. 54(1), 409 (2009).

4 Y. Kuo and H. Nominanda , Mat. Res. Soc. Symp. Proc. Vol. 1066, Warrendale, PA, 1066–A08 (2008).

5 D. Kahng and S. M. Sze , Bell Syst. Tech. J. 46 1283 (1967).

7 Y. Kuo , SPIE Proc. 1456, 288 (1991).

8 Y. Kuo and M. Crowder , J. Electrochem. Soc. 139(2), 548 (1992).

9 Y. Kuo , J. Electrochem. Soc. 142(1), 186 (1995).

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MRS Online Proceedings Library (OPL)
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  • EISSN: 1946-4274
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