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Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

Published online by Cambridge University Press:  21 March 2011

X. Duan ,
K. Kisslinger ,
L. Mayes ,
S. Ruby  and
J. Barrett
X. Duan
Affiliation:
National Semiconductor Corp., South Portland, ME 04106 MIT, Dept. of Materials Science and Engineering, Cambridge, MA 02139
K. Kisslinger
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
L. Mayes
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
S. Ruby
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
J. Barrett
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
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Abstract

The Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 654: Symposia AA – Structure-Property Relationships of Oxide Surfaces & Interfaces , 2000 , AA3.43.1
Copyright
Copyright © Materials Research Society 2001

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References

[1] Muller, D. A., Sorsch, T., Moccio, S., Baumann, F. H., Evans-Lutterodt, K. and Timp, G.; Nature 1999, v 399, n 6738, p 758.Google Scholar
[2] Cho, W., Kim, Y., Kim, E. and Kim, H.; Japanese Journal of Applied Physics, 1999, Part 1, v 38, n 1A, p 12.Google Scholar
[3].Eriguchi, K., Harada, Y. and Niwa, M.; Technical Digest - Proceedings of the 1998 IEEE International Electron Devices Meeting, P 175.Google Scholar
[4].Cho, W., Kim, E., Kang, J., Rha, K. and Kim, H.; Solid-State Electronics, 1998, v 42, n 4, p557.Google Scholar
[5].Yamada, R., Yugami, J. and Ohkura, M., Digest of Technical Papers -Proceedings of the 1997 Symposium on VLSI Technology; June 1997 Kyoto, Japan, P 147, 0743-1562, DTPTEW.Google Scholar
[6].Wolf, S. and Tauber, R. N., “Silicon Processing for the VLSI ERA”, v 1, 1986, Lattice Press, California, USA, P 531.Google Scholar
[7].Bayoumi, A., Fischer-Colbrie, A., Parker, R., Cox, M. and Greene, W.; Science and Technology of Semiconductor Surface Preparation, Proceedings of the 1997 MRS Spring Meeting, 1997, v 477, p 247.Google Scholar
[8].Ma, Y., Green, M. L., Torek, K., Ruzyllo, J., Opila, R., Konstadinidis, K., Siconolfi, D. and Brasen, D.; Journal of the Electrochemical Society, 1995, v 142, n 11, p L217.Google Scholar
[9].Ericsson, P., Bengtsson, S. and Sodervall, U.; Doktorsavhandlingar vid Chalmers Tekniska Hogskola, 1997, n 1322, p 0346.Google Scholar
[10].Bean, K. E.; “Anisotropic Etching of Si”, IEEE Trans. Electron Devices, 1978, ED–25, p 1185.Google Scholar