Skip to main content

Investigation of Mechanical Stresses in Underlying Silicon due to Lead-Tin Solder Bumps via Synchrotron X-Ray Topography and Finite Element Analysis

  • J. Kanatharana (a1), J.J. Pérez-Camacho (a2), T. Buckley (a2), P.J. McNally (a1), T. Tuomi (a3), A.N. Danilewsky (a4), M. O'Hare (a1), D. Lowney (a1) and W. Chen (a1)...

Solder based flip-chip packaging has prompted interest in many integrated circuit (IC)packaging applications due to its many advantages in terms of cost, package size, electricalperformance, input/output density, etc. The ball grid array (BGA) is one of the most commonflip-chip packaging techniques used for microprocessor applications. However, mechanicalstresses induced by the flip-chip process can impact adversely on the reliability of production.

White beam synchrotron x-ray topography (SXRT), a non-destructive technique, has beenemployed to investigate the spatial extent of strain fields imposed on the underlying siliconsubstrate for Intelν®Pentiumν®III microprocessors due to the lead-tin solder bump process for BGApackaging. Large area and section back-reflection SXRT images were taken before and after asimulation of the reflow process at 350°C in atmosphere. The presence of induced strain fields inthe Si substrate due to the overlying bump structures has been observed via the extinction contrasteffect in these x-ray topographs. In addition, orientational contrast effects have also been foundafter the reflow process due to the severe stresses in the underlying silicon beneath the lead bumps.The estimated magnitudes of stress, ∣σ∣, imposed on the underlying silicon were calculated to be100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the leadbumps were removed from the wafer, which confirms that the bumps are indeed a major source ofstrain in the underlying Si. Finite element analysis (FEA) has also been performed in 2-D planestrain mode. The magnitudes and spatial distribution of the stresses after the reflow process are ingood agreement with the SXRT results.

Hide All
1. Blackwell, G.R., Chapter 4: Direct Chip Attach, The Electronic Packaging Handbook, ed. Blackwell, G.R.(CRC Press, 1999).
2. Nagesh, V.K., Peddada, R., Ramalingam, S., Sur, B. and Tai, A., Challenges of Flip Chip on Organic substrateAssembly Technology, IEEE Proceeding 1999 Electronics Component and technology conference, pp.975978 (1999).
3. McNally, P.J., Curley, J., Bolt, M., Reader, A., Tuomi, T., Rantamaki, R., Danilewsky, A. and wolf, I. De, Monitoring of Stress Reduction in Shallow Trench Isolation CMOS structures Via Synchrotron X-rayTopography, Electrical Data and Raman Spectroscopy, Journal of Materials Science: Materials inElectronics 10, pp.351358 (1999).
4. Wang, J., Qian, Z. and Liu, S., Process Induced Stresses of a Flip-Chip Packaging by Sequential ProcessingModeling Technique, Transactions of the ASME, Journal of Electronic Packaging 120, pp.309313 (1998).
5. Yao, Q. and Qu, J., Three-Dimensional Versus Two-Dimensional Finite Element Modeling of Flip-ChipPackages, Transactions of the ASME, Journal of Electronic Packaging 121, pp.196201 (1999).
6. Variyam, M.N., Xie, W. and Sitaraman, S.K., Role of Out-of-Plane Coefficient of Thermal Expansion inElectronic Packaging Modeling, Transactions of the ASME, Journal of Electronic Packaging 122, pp.121127 (2000).
7. Tuomi, T., Naukkarinen, K. and Rabe, P., Use of Synchrotron Radiation in X-ray Diffraction Topography,Phys. Stat. Sol. A 25, pp.93106 (1974).
8. McNally, P.J., Curley, J., Krier, A., Mao, Y., Richardson, J., Tuomi, T., Taskinen, M., Rantamaki, R., Prieurand, E. Danilewsky, A., An Evaluation of Liquid Phase Epitaxial InGaAs/InAs Heterostructures for InfraredDevices Using Synchrotron X-ray Topography, Semiconductor Science and Technology 13, pp.345349(1998).
9. Rantamaki, R., X-ray Topography of Semiconductors using Synchrotron Radiation, HD. Sci Thesis, Optoelectronics Laboratory, Department of Electrical and Communications Engineering, HelsinkiUniversity of Technology, pp.1112 (1999).
10. Brand, A., Haranahalli, A., Hsieh, N., Lin, Y.C., Sery, G., Stenton, N., Woo, B.J., Ahmed, S., Bohr, M., Yang, S., “Intel's 0.25 Micron, 2.0 Volts Logic Process Technology”, Intel Technology Journal, 3rd Quarter 1998.
11. Meieran, E.S. and Blech, I.A., X-ray Extinction Contrast Topography of Silicon Strained by Thin SurfaceFilms, Journal of Applied Physics 36, pp.31623167 (1965).
12. Karilahti, M., Tuomi, T., Taskinen, M., Tulkki, J., Lipsanen, H. and McNally, P., Synchrotron X-rayTopographic Study of Strain in Silicon Wafers with Intergrated Circuits, IL Nuovo Cimento, 19D(2-4), pp.181184 (1997).
13. King, J.A., Materials, Handbook for Hybrid Microelectronics (Artech, USA, 1988).
14. Quickfield™,
Recommend this journal

Email your librarian or administrator to recommend adding this journal to your organisation's collection.

MRS Online Proceedings Library (OPL)
  • ISSN: -
  • EISSN: 1946-4274
  • URL: /core/journals/mrs-online-proceedings-library-archive
Please enter your name
Please enter a valid email address
Who would you like to send this to? *


Full text views

Total number of HTML views: 0
Total number of PDF views: 0 *
Loading metrics...

Abstract views

Total abstract views: 0 *
Loading metrics...

* Views captured on Cambridge Core between <date>. This data will be updated every 24 hours.

Usage data cannot currently be displayed